1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
3 ; For formal arguments, we have the following vector type promotion,
4 ; v2i8 is promoted to v2i32(f64)
5 ; v2i16 is promoted to v2i32(f64)
6 ; v4i8 is promoted to v4i16(f64)
7 ; v8i1 is promoted to v8i16(f128)
9 define <2 x i8> @test_sext_inreg_v2i8i16(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
10 ; CHECK-LABEL: test_sext_inreg_v2i8i16
11 ; CHECK: sshll v0.8h, v0.8b, #0
12 ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
13 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
14 ; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
15 %1 = sext <2 x i8> %v1 to <2 x i16>
16 %2 = sext <2 x i8> %v2 to <2 x i16>
17 %3 = shufflevector <2 x i16> %1, <2 x i16> %2, <2 x i32> <i32 0, i32 2>
18 %4 = trunc <2 x i16> %3 to <2 x i8>
22 define <2 x i8> @test_sext_inreg_v2i8i16_2(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
23 ; CHECK-LABEL: test_sext_inreg_v2i8i16_2
24 ; CHECK: sshll v0.8h, v0.8b, #0
25 ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
26 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
27 ; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
28 %a1 = shl <2 x i32> %v1, <i32 24, i32 24>
29 %a2 = ashr <2 x i32> %a1, <i32 24, i32 24>
30 %b1 = shl <2 x i32> %v2, <i32 24, i32 24>
31 %b2 = ashr <2 x i32> %b1, <i32 24, i32 24>
32 %c = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>
33 %d = trunc <2 x i32> %c to <2 x i8>
37 define <2 x i8> @test_sext_inreg_v2i8i32(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
38 ; CHECK-LABEL: test_sext_inreg_v2i8i32
39 ; CHECK: sshll v0.8h, v0.8b, #0
40 ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
41 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
42 ; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
43 %1 = sext <2 x i8> %v1 to <2 x i32>
44 %2 = sext <2 x i8> %v2 to <2 x i32>
45 %3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2>
46 %4 = trunc <2 x i32> %3 to <2 x i8>
50 define <2 x i8> @test_sext_inreg_v2i8i64(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
51 ; CHECK-LABEL: test_sext_inreg_v2i8i64
52 ; CHECK: ushll v1.2d, v1.2s, #0
53 ; CHECK: ushll v0.2d, v0.2s, #0
54 ; CHECK: shl v0.2d, v0.2d, #56
55 ; CHECK: sshr v0.2d, v0.2d, #56
56 ; CHECK: shl v1.2d, v1.2d, #56
57 ; CHECK: sshr v1.2d, v1.2d, #56
58 %1 = sext <2 x i8> %v1 to <2 x i64>
59 %2 = sext <2 x i8> %v2 to <2 x i64>
60 %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
61 %4 = trunc <2 x i64> %3 to <2 x i8>
65 define <4 x i8> @test_sext_inreg_v4i8i16(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
66 ; CHECK-LABEL: test_sext_inreg_v4i8i16
67 ; CHECK: sshll v0.8h, v0.8b, #0
68 ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
69 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
70 ; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
71 %1 = sext <4 x i8> %v1 to <4 x i16>
72 %2 = sext <4 x i8> %v2 to <4 x i16>
73 %3 = shufflevector <4 x i16> %1, <4 x i16> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
74 %4 = trunc <4 x i16> %3 to <4 x i8>
78 define <4 x i8> @test_sext_inreg_v4i8i16_2(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
79 ; CHECK-LABEL: test_sext_inreg_v4i8i16_2
80 ; CHECK: sshll v0.8h, v0.8b, #0
81 ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
82 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
83 ; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
84 %a1 = shl <4 x i16> %v1, <i16 8, i16 8, i16 8, i16 8>
85 %a2 = ashr <4 x i16> %a1, <i16 8, i16 8, i16 8, i16 8>
86 %b1 = shl <4 x i16> %v2, <i16 8, i16 8, i16 8, i16 8>
87 %b2 = ashr <4 x i16> %b1, <i16 8, i16 8, i16 8, i16 8>
88 %c = shufflevector <4 x i16> %a2, <4 x i16> %b2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
89 %d = trunc <4 x i16> %c to <4 x i8>
93 define <4 x i8> @test_sext_inreg_v4i8i32(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
94 ; CHECK-LABEL: test_sext_inreg_v4i8i32
95 ; CHECK: ushll v1.4s, v1.4h, #0
96 ; CHECK: ushll v0.4s, v0.4h, #0
97 ; CHECK: shl v0.4s, v0.4s, #24
98 ; CHECK: sshr v0.4s, v0.4s, #24
99 ; CHECK: shl v1.4s, v1.4s, #24
100 ; CHECK: sshr v1.4s, v1.4s, #24
101 %1 = sext <4 x i8> %v1 to <4 x i32>
102 %2 = sext <4 x i8> %v2 to <4 x i32>
103 %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
104 %4 = trunc <4 x i32> %3 to <4 x i8>
108 define <8 x i8> @test_sext_inreg_v8i8i16(<8 x i8> %v1, <8 x i8> %v2) nounwind readnone {
109 ; CHECK-LABEL: test_sext_inreg_v8i8i16
110 ; CHECK: sshll v0.8h, v0.8b, #0
111 ; CHECK: sshll v1.8h, v1.8b, #0
112 %1 = sext <8 x i8> %v1 to <8 x i16>
113 %2 = sext <8 x i8> %v2 to <8 x i16>
114 %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
115 %4 = trunc <8 x i16> %3 to <8 x i8>
119 define <8 x i1> @test_sext_inreg_v8i1i16(<8 x i1> %v1, <8 x i1> %v2) nounwind readnone {
120 ; CHECK-LABEL: test_sext_inreg_v8i1i16
121 ; CHECK: ushll v1.8h, v1.8b, #0
122 ; CHECK: ushll v0.8h, v0.8b, #0
123 ; CHECK: shl v0.8h, v0.8h, #15
124 ; CHECK: sshr v0.8h, v0.8h, #15
125 ; CHECK: shl v1.8h, v1.8h, #15
126 ; CHECK: sshr v1.8h, v1.8h, #15
127 %1 = sext <8 x i1> %v1 to <8 x i16>
128 %2 = sext <8 x i1> %v2 to <8 x i16>
129 %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
130 %4 = trunc <8 x i16> %3 to <8 x i1>
134 define <2 x i16> @test_sext_inreg_v2i16i32(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
135 ; CHECK-LABEL: test_sext_inreg_v2i16i32
136 ; CHECK: sshll v0.4s, v0.4h, #0
137 ; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
138 ; CHECK-NEXT: sshll v1.4s, v1.4h, #0
139 ; CHECK-NEXT: uzp1 v1.4s, v1.4s, v1.4s
140 %1 = sext <2 x i16> %v1 to <2 x i32>
141 %2 = sext <2 x i16> %v2 to <2 x i32>
142 %3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2>
143 %4 = trunc <2 x i32> %3 to <2 x i16>
147 define <2 x i16> @test_sext_inreg_v2i16i32_2(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
148 ; CHECK-LABEL: test_sext_inreg_v2i16i32_2
149 ; CHECK: sshll v0.4s, v0.4h, #0
150 ; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
151 ; CHECK-NEXT: sshll v1.4s, v1.4h, #0
152 ; CHECK-NEXT: uzp1 v1.4s, v1.4s, v1.4s
153 %a1 = shl <2 x i32> %v1, <i32 16, i32 16>
154 %a2 = ashr <2 x i32> %a1, <i32 16, i32 16>
155 %b1 = shl <2 x i32> %v2, <i32 16, i32 16>
156 %b2 = ashr <2 x i32> %b1, <i32 16, i32 16>
157 %c = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>
158 %d = trunc <2 x i32> %c to <2 x i16>
162 define <2 x i16> @test_sext_inreg_v2i16i64(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
163 ; CHECK-LABEL: test_sext_inreg_v2i16i64
164 ; CHECK: ushll v1.2d, v1.2s, #0
165 ; CHECK: ushll v0.2d, v0.2s, #0
166 ; CHECK: shl v0.2d, v0.2d, #48
167 ; CHECK: sshr v0.2d, v0.2d, #48
168 ; CHECK: shl v1.2d, v1.2d, #48
169 ; CHECK: sshr v1.2d, v1.2d, #48
170 %1 = sext <2 x i16> %v1 to <2 x i64>
171 %2 = sext <2 x i16> %v2 to <2 x i64>
172 %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
173 %4 = trunc <2 x i64> %3 to <2 x i16>
177 define <4 x i16> @test_sext_inreg_v4i16i32(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
178 ; CHECK-LABEL: test_sext_inreg_v4i16i32
179 ; CHECK: sshll v0.4s, v0.4h, #0
180 ; CHECK: sshll v1.4s, v1.4h, #0
181 %1 = sext <4 x i16> %v1 to <4 x i32>
182 %2 = sext <4 x i16> %v2 to <4 x i32>
183 %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
184 %4 = trunc <4 x i32> %3 to <4 x i16>
188 define <2 x i32> @test_sext_inreg_v2i32i64(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
189 ; CHECK-LABEL: test_sext_inreg_v2i32i64
190 ; CHECK: sshll v0.2d, v0.2s, #0
191 ; CHECK: sshll v1.2d, v1.2s, #0
192 %1 = sext <2 x i32> %v1 to <2 x i64>
193 %2 = sext <2 x i32> %v2 to <2 x i64>
194 %3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
195 %4 = trunc <2 x i64> %3 to <2 x i32>