1 ; RUN: llc < %s -mtriple aarch64-apple-darwin | FileCheck %s
3 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
8 define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0 {
9 ; CHECK-LABEL: test_copysign_v1f32_v1f32:
11 ; CHECK-NEXT: mov s2, v1[1]
12 ; CHECK-NEXT: mov s3, v0[1]
13 ; CHECK-NEXT: movi.4s v4, #0x80, lsl #24
14 ; CHECK-NEXT: bit.16b v3, v2, v4
15 ; CHECK-NEXT: bit.16b v0, v1, v4
16 ; CHECK-NEXT: ins.s v0[1], v3[0]
18 %r = call <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %b)
22 ; WidenVecRes mismatched
23 define <1 x float> @test_copysign_v1f32_v1f64(<1 x float> %a, <1 x double> %b) #0 {
24 ; CHECK-LABEL: test_copysign_v1f32_v1f64:
26 ; CHECK-NEXT: fcvt s1, d1
27 ; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
28 ; CHECK-NEXT: bit.16b v0, v1, v2
30 %tmp0 = fptrunc <1 x double> %b to <1 x float>
31 %r = call <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %tmp0)
35 declare <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %b) #0
40 define <1 x double> @test_copysign_v1f64_v1f32(<1 x double> %a, <1 x float> %b) #0 {
41 ; CHECK-LABEL: test_copysign_v1f64_v1f32:
43 ; CHECK-NEXT: fcvt d1, s1
44 ; CHECK-NEXT: movi.2d v2, #0000000000000000
45 ; CHECK-NEXT: fneg.2d v2, v2
46 ; CHECK-NEXT: bit.16b v0, v1, v2
48 %tmp0 = fpext <1 x float> %b to <1 x double>
49 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %tmp0)
53 define <1 x double> @test_copysign_v1f64_v1f64(<1 x double> %a, <1 x double> %b) #0 {
54 ; CHECK-LABEL: test_copysign_v1f64_v1f64:
56 ; CHECK-NEXT: movi.2d v2, #0000000000000000
57 ; CHECK-NEXT: fneg.2d v2, v2
58 ; CHECK-NEXT: bit.16b v0, v1, v2
60 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b)
64 declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0
68 define <2 x float> @test_copysign_v2f32_v2f32(<2 x float> %a, <2 x float> %b) #0 {
69 ; CHECK-LABEL: test_copysign_v2f32_v2f32:
71 ; CHECK-NEXT: mov s2, v1[1]
72 ; CHECK-NEXT: mov s3, v0[1]
73 ; CHECK-NEXT: movi.4s v4, #0x80, lsl #24
74 ; CHECK-NEXT: bit.16b v3, v2, v4
75 ; CHECK-NEXT: bit.16b v0, v1, v4
76 ; CHECK-NEXT: ins.s v0[1], v3[0]
78 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b)
82 define <2 x float> @test_copysign_v2f32_v2f64(<2 x float> %a, <2 x double> %b) #0 {
83 ; CHECK-LABEL: test_copysign_v2f32_v2f64:
85 ; CHECK-NEXT: mov d2, v1[1]
86 ; CHECK-NEXT: mov s3, v0[1]
87 ; CHECK-NEXT: movi.4s v4, #0x80, lsl #24
88 ; CHECK-NEXT: fcvt s1, d1
89 ; CHECK-NEXT: fcvt s2, d2
90 ; CHECK-NEXT: bit.16b v3, v2, v4
91 ; CHECK-NEXT: bit.16b v0, v1, v4
92 ; CHECK-NEXT: ins.s v0[1], v3[0]
94 %tmp0 = fptrunc <2 x double> %b to <2 x float>
95 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %tmp0)
99 declare <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) #0
103 define <4 x float> @test_copysign_v4f32_v4f32(<4 x float> %a, <4 x float> %b) #0 {
104 ; CHECK-LABEL: test_copysign_v4f32_v4f32:
106 ; CHECK-NEXT: mov s2, v1[1]
107 ; CHECK-NEXT: mov s3, v0[1]
108 ; CHECK-NEXT: movi.4s v4, #0x80, lsl #24
109 ; CHECK-NEXT: mov s5, v0[2]
110 ; CHECK-NEXT: bit.16b v3, v2, v4
111 ; CHECK-NEXT: mov s2, v0[3]
112 ; CHECK-NEXT: mov s6, v1[2]
113 ; CHECK-NEXT: bit.16b v0, v1, v4
114 ; CHECK-NEXT: bit.16b v5, v6, v4
115 ; CHECK-NEXT: mov s1, v1[3]
116 ; CHECK-NEXT: ins.s v0[1], v3[0]
117 ; CHECK-NEXT: ins.s v0[2], v5[0]
118 ; CHECK-NEXT: bit.16b v2, v1, v4
119 ; CHECK-NEXT: ins.s v0[3], v2[0]
121 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)
126 define <4 x float> @test_copysign_v4f32_v4f64(<4 x float> %a, <4 x double> %b) #0 {
127 ; CHECK-LABEL: test_copysign_v4f32_v4f64:
129 ; CHECK-NEXT: mov s3, v0[1]
130 ; CHECK-NEXT: mov d4, v1[1]
131 ; CHECK-NEXT: movi.4s v5, #0x80, lsl #24
132 ; CHECK-NEXT: fcvt s1, d1
133 ; CHECK-NEXT: mov s6, v0[2]
134 ; CHECK-NEXT: mov s7, v0[3]
135 ; CHECK-NEXT: fcvt s16, d2
136 ; CHECK-NEXT: bit.16b v0, v1, v5
137 ; CHECK-NEXT: bit.16b v6, v16, v5
138 ; CHECK-NEXT: fcvt s1, d4
139 ; CHECK-NEXT: bit.16b v3, v1, v5
140 ; CHECK-NEXT: mov d1, v2[1]
141 ; CHECK-NEXT: fcvt s1, d1
142 ; CHECK-NEXT: ins.s v0[1], v3[0]
143 ; CHECK-NEXT: ins.s v0[2], v6[0]
144 ; CHECK-NEXT: bit.16b v7, v1, v5
145 ; CHECK-NEXT: ins.s v0[3], v7[0]
147 %tmp0 = fptrunc <4 x double> %b to <4 x float>
148 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)
152 declare <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) #0
156 define <2 x double> @test_copysign_v2f64_v232(<2 x double> %a, <2 x float> %b) #0 {
157 ; CHECK-LABEL: test_copysign_v2f64_v232:
159 ; CHECK-NEXT: mov d2, v0[1]
160 ; CHECK-NEXT: mov s3, v1[1]
161 ; CHECK-NEXT: movi.2d v4, #0000000000000000
162 ; CHECK-NEXT: fcvt d1, s1
163 ; CHECK-NEXT: fcvt d3, s3
164 ; CHECK-NEXT: fneg.2d v4, v4
165 ; CHECK-NEXT: bit.16b v2, v3, v4
166 ; CHECK-NEXT: bit.16b v0, v1, v4
167 ; CHECK-NEXT: ins.d v0[1], v2[0]
169 %tmp0 = fpext <2 x float> %b to <2 x double>
170 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %tmp0)
174 define <2 x double> @test_copysign_v2f64_v2f64(<2 x double> %a, <2 x double> %b) #0 {
175 ; CHECK-LABEL: test_copysign_v2f64_v2f64:
177 ; CHECK-NEXT: mov d2, v1[1]
178 ; CHECK-NEXT: mov d3, v0[1]
179 ; CHECK-NEXT: movi.2d v4, #0000000000000000
180 ; CHECK-NEXT: fneg.2d v4, v4
181 ; CHECK-NEXT: bit.16b v3, v2, v4
182 ; CHECK-NEXT: bit.16b v0, v1, v4
183 ; CHECK-NEXT: ins.d v0[1], v3[0]
185 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b)
189 declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0
193 ; SplitVecRes mismatched
194 define <4 x double> @test_copysign_v4f64_v4f32(<4 x double> %a, <4 x float> %b) #0 {
195 ; CHECK-LABEL: test_copysign_v4f64_v4f32:
197 ; CHECK-NEXT: ext.16b v3, v2, v2, #8
198 ; CHECK-NEXT: mov d4, v0[1]
199 ; CHECK-NEXT: mov s5, v2[1]
200 ; CHECK-NEXT: movi.2d v6, #0000000000000000
201 ; CHECK-NEXT: fcvt d2, s2
202 ; CHECK-NEXT: fcvt d5, s5
203 ; CHECK-NEXT: fneg.2d v6, v6
204 ; CHECK-NEXT: bit.16b v4, v5, v6
205 ; CHECK-NEXT: mov d5, v1[1]
206 ; CHECK-NEXT: bit.16b v0, v2, v6
207 ; CHECK-NEXT: mov s2, v3[1]
208 ; CHECK-NEXT: fcvt d3, s3
209 ; CHECK-NEXT: fcvt d2, s2
210 ; CHECK-NEXT: ins.d v0[1], v4[0]
211 ; CHECK-NEXT: bit.16b v5, v2, v6
212 ; CHECK-NEXT: bit.16b v1, v3, v6
213 ; CHECK-NEXT: ins.d v1[1], v5[0]
215 %tmp0 = fpext <4 x float> %b to <4 x double>
216 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0)
221 define <4 x double> @test_copysign_v4f64_v4f64(<4 x double> %a, <4 x double> %b) #0 {
222 ; CHECK-LABEL: test_copysign_v4f64_v4f64:
224 ; CHECK-NEXT: mov d4, v2[1]
225 ; CHECK-NEXT: mov d5, v0[1]
226 ; CHECK-NEXT: movi.2d v6, #0000000000000000
227 ; CHECK-NEXT: fneg.2d v6, v6
228 ; CHECK-NEXT: bit.16b v5, v4, v6
229 ; CHECK-NEXT: mov d4, v3[1]
230 ; CHECK-NEXT: bit.16b v0, v2, v6
231 ; CHECK-NEXT: mov d2, v1[1]
232 ; CHECK-NEXT: bit.16b v2, v4, v6
233 ; CHECK-NEXT: bit.16b v1, v3, v6
234 ; CHECK-NEXT: ins.d v0[1], v5[0]
235 ; CHECK-NEXT: ins.d v1[1], v2[0]
237 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b)
241 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0
243 attributes #0 = { nounwind }