1 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
2 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
4 ; Tests for indirect addressing on SI, which is implemented using dynamic
7 ; CHECK-LABEL: {{^}}extract_w_offset:
9 ; CHECK-NEXT: v_movrels_b32_e32
10 define void @extract_w_offset(float addrspace(1)* %out, i32 %in) {
13 %1 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %0
14 store float %1, float addrspace(1)* %out
18 ; CHECK-LABEL: {{^}}extract_wo_offset:
20 ; CHECK-NEXT: v_movrels_b32_e32
21 define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) {
23 %0 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %in
24 store float %0, float addrspace(1)* %out
28 ; CHECK-LABEL: {{^}}extract_neg_offset_sgpr:
29 ; The offset depends on the register that holds the first element of the vector.
30 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
31 ; CHECK: v_movrels_b32_e32 v{{[0-9]}}, v0
32 define void @extract_neg_offset_sgpr(i32 addrspace(1)* %out, i32 %offset) {
34 %index = add i32 %offset, -512
35 %value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
36 store i32 %value, i32 addrspace(1)* %out
40 ; CHECK-LABEL: {{^}}extract_neg_offset_vgpr:
41 ; The offset depends on the register that holds the first element of the vector.
42 ; CHECK: v_readfirstlane_b32
43 ; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
44 ; CHECK-NEXT: v_movrels_b32_e32 v{{[0-9]}}, v0
45 ; CHECK: s_cbranch_execnz
46 define void @extract_neg_offset_vgpr(i32 addrspace(1)* %out) {
48 %id = call i32 @llvm.r600.read.tidig.x() #1
49 %index = add i32 %id, -512
50 %value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
51 store i32 %value, i32 addrspace(1)* %out
55 ; CHECK-LABEL: {{^}}insert_w_offset:
57 ; CHECK-NEXT: v_movreld_b32_e32
58 define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
61 %1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0
62 %2 = extractelement <4 x float> %1, i32 2
63 store float %2, float addrspace(1)* %out
67 ; CHECK-LABEL: {{^}}insert_wo_offset:
69 ; CHECK-NEXT: v_movreld_b32_e32
70 define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
72 %0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
73 %1 = extractelement <4 x float> %0, i32 2
74 store float %1, float addrspace(1)* %out
78 ; CHECK-LABEL: {{^}}insert_neg_offset_sgpr:
79 ; The offset depends on the register that holds the first element of the vector.
80 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
81 ; CHECK: v_movreld_b32_e32 v0, v{{[0-9]}}
82 define void @insert_neg_offset_sgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out, i32 %offset) {
84 %index = add i32 %offset, -512
85 %value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
86 store <4 x i32> %value, <4 x i32> addrspace(1)* %out
90 ; CHECK-LABEL: {{^}}insert_neg_offset_vgpr:
91 ; The offset depends on the register that holds the first element of the vector.
92 ; CHECK: v_readfirstlane_b32
93 ; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
94 ; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
95 ; CHECK: s_cbranch_execnz
96 define void @insert_neg_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
98 %id = call i32 @llvm.r600.read.tidig.x() #1
99 %index = add i32 %id, -512
100 %value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
101 store <4 x i32> %value, <4 x i32> addrspace(1)* %out
105 ; CHECK-LABEL: {{^}}insert_neg_inline_offset_vgpr:
106 ; The offset depends on the register that holds the first element of the vector.
107 ; CHECK: v_readfirstlane_b32
108 ; CHECK: s_add_i32 m0, m0, -{{[0-9]+}}
109 ; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
110 ; CHECK: s_cbranch_execnz
111 define void @insert_neg_inline_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
113 %id = call i32 @llvm.r600.read.tidig.x() #1
114 %index = add i32 %id, -16
115 %value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
116 store <4 x i32> %value, <4 x i32> addrspace(1)* %out
120 declare i32 @llvm.r600.read.tidig.x() #1
121 attributes #1 = { nounwind readnone }