1 ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s
2 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}vector_umin:
6 define void @vector_umin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
8 %load = load i32, i32 addrspace(1)* %in, align 4
9 %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %load)
10 %bc = bitcast i32 %min to float
11 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
15 ; SI-LABEL: {{^}}scalar_umin:
17 define void @scalar_umin(i32 %p0, i32 %p1) #0 {
19 %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1)
20 %bc = bitcast i32 %min to float
21 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
25 ; SI-LABEL: {{^}}trunc_zext_umin:
26 ; SI: buffer_load_ubyte [[VREG:v[0-9]+]],
27 ; SI: v_min_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]]
29 ; SI: buffer_store_short [[RESULT]],
30 define void @trunc_zext_umin(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
31 %tmp5 = load i8, i8 addrspace(1)* %src, align 1
32 %tmp2 = zext i8 %tmp5 to i32
33 %tmp3 = tail call i32 @llvm.AMDGPU.umin(i32 %tmp2, i32 0) nounwind readnone
34 %tmp4 = trunc i32 %tmp3 to i8
35 %tmp6 = zext i8 %tmp4 to i16
36 store i16 %tmp6, i16 addrspace(1)* %out, align 2
40 ; Function Attrs: readnone
41 declare i32 @llvm.AMDGPU.umin(i32, i32) #1
43 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
45 attributes #0 = { nounwind }
46 attributes #1 = { nounwind readnone }
48 !0 = !{!"const", null, i32 1}