1 ;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s
4 ; CHECK-LABEL: {{^}}v1:
5 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 13
6 define void @v1(i32 %a1) #0 {
8 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
9 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
10 %2 = extractelement <4 x float> %1, i32 0
11 %3 = extractelement <4 x float> %1, i32 2
12 %4 = extractelement <4 x float> %1, i32 3
13 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
17 ; CHECK-LABEL: {{^}}v2:
18 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 11
19 define void @v2(i32 %a1) #0 {
21 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
22 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
23 %2 = extractelement <4 x float> %1, i32 0
24 %3 = extractelement <4 x float> %1, i32 1
25 %4 = extractelement <4 x float> %1, i32 3
26 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
30 ; CHECK-LABEL: {{^}}v3:
31 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14
32 define void @v3(i32 %a1) #0 {
34 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
35 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
36 %2 = extractelement <4 x float> %1, i32 1
37 %3 = extractelement <4 x float> %1, i32 2
38 %4 = extractelement <4 x float> %1, i32 3
39 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
43 ; CHECK-LABEL: {{^}}v4:
44 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 7
45 define void @v4(i32 %a1) #0 {
47 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
48 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
49 %2 = extractelement <4 x float> %1, i32 0
50 %3 = extractelement <4 x float> %1, i32 1
51 %4 = extractelement <4 x float> %1, i32 2
52 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
56 ; CHECK-LABEL: {{^}}v5:
57 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10
58 define void @v5(i32 %a1) #0 {
60 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
61 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
62 %2 = extractelement <4 x float> %1, i32 1
63 %3 = extractelement <4 x float> %1, i32 3
64 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
68 ; CHECK-LABEL: {{^}}v6:
69 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 6
70 define void @v6(i32 %a1) #0 {
72 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
73 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
74 %2 = extractelement <4 x float> %1, i32 1
75 %3 = extractelement <4 x float> %1, i32 2
76 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
80 ; CHECK-LABEL: {{^}}v7:
81 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 9
82 define void @v7(i32 %a1) #0 {
84 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
85 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
86 %2 = extractelement <4 x float> %1, i32 0
87 %3 = extractelement <4 x float> %1, i32 3
88 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
92 declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
94 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
96 attributes #0 = { "ShaderType"="0" }