1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}s_movk_i32_k0:
5 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}}
6 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 1{{$}}
7 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
8 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
9 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
11 define void @s_movk_i32_k0(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
12 %loada = load i64, i64 addrspace(1)* %a, align 4
13 %or = or i64 %loada, 4295032831 ; ((1 << 16) - 1) | (1 << 32)
14 store i64 %or, i64 addrspace(1)* %out
18 ; SI-LABEL: {{^}}s_movk_i32_k1:
19 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}}
20 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 1{{$}}
21 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
22 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
23 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
25 define void @s_movk_i32_k1(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
26 %loada = load i64, i64 addrspace(1)* %a, align 4
27 %or = or i64 %loada, 4295000063 ; ((1 << 15) - 1) | (1 << 32)
28 store i64 %or, i64 addrspace(1)* %out
32 ; SI-LABEL: {{^}}s_movk_i32_k2:
33 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}}
34 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 64{{$}}
35 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
36 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
37 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
39 define void @s_movk_i32_k2(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
40 %loada = load i64, i64 addrspace(1)* %a, align 4
41 %or = or i64 %loada, 274877939711 ; ((1 << 15) - 1) | (64 << 32)
42 store i64 %or, i64 addrspace(1)* %out
46 ; SI-LABEL: {{^}}s_movk_i32_k3:
47 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}}
48 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 1{{$}}
49 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
50 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
51 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
53 define void @s_movk_i32_k3(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
54 %loada = load i64, i64 addrspace(1)* %a, align 4
55 %or = or i64 %loada, 4295000064 ; (1 << 15) | (1 << 32)
56 store i64 %or, i64 addrspace(1)* %out
60 ; SI-LABEL: {{^}}s_movk_i32_k4:
61 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x20000{{$}}
62 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 1{{$}}
63 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
64 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
65 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
67 define void @s_movk_i32_k4(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
68 %loada = load i64, i64 addrspace(1)* %a, align 4
69 %or = or i64 %loada, 4295098368 ; (1 << 17) | (1 << 32)
70 store i64 %or, i64 addrspace(1)* %out
74 ; SI-LABEL: {{^}}s_movk_i32_k5:
75 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0xffef{{$}}
76 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0xff00ffff{{$}}
77 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
78 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
79 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
81 define void @s_movk_i32_k5(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
82 %loada = load i64, i64 addrspace(1)* %a, align 4
83 %or = or i64 %loada, 18374967954648334319 ; -17 & 0xff00ffffffffffff
84 store i64 %or, i64 addrspace(1)* %out
88 ; SI-LABEL: {{^}}s_movk_i32_k6:
89 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x41{{$}}
90 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 63{{$}}
91 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
92 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
93 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
95 define void @s_movk_i32_k6(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
96 %loada = load i64, i64 addrspace(1)* %a, align 4
97 %or = or i64 %loada, 270582939713 ; 65 | (63 << 32)
98 store i64 %or, i64 addrspace(1)* %out
102 ; SI-LABEL: {{^}}s_movk_i32_k7:
103 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x2000{{$}}
104 ; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x4000{{$}}
105 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
106 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
107 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
109 define void @s_movk_i32_k7(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
110 %loada = load i64, i64 addrspace(1)* %a, align 4
111 %or = or i64 %loada, 70368744185856; ((1 << 13)) | ((1 << 14) << 32)
112 store i64 %or, i64 addrspace(1)* %out
117 ; SI-LABEL: {{^}}s_movk_i32_k8:
118 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}}
119 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
120 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
121 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
122 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
124 define void @s_movk_i32_k8(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
125 %loada = load i64, i64 addrspace(1)* %a, align 4
126 %or = or i64 %loada, 1229782942255906816 ; 0x11111111ffff8000
127 store i64 %or, i64 addrspace(1)* %out
131 ; SI-LABEL: {{^}}s_movk_i32_k9:
132 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8001{{$}}
133 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
134 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
135 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
136 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
138 define void @s_movk_i32_k9(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
139 %loada = load i64, i64 addrspace(1)* %a, align 4
140 %or = or i64 %loada, 1229782942255906817 ; 0x11111111ffff8001
141 store i64 %or, i64 addrspace(1)* %out
145 ; SI-LABEL: {{^}}s_movk_i32_k10:
146 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8888{{$}}
147 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
148 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
149 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
150 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
152 define void @s_movk_i32_k10(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
153 %loada = load i64, i64 addrspace(1)* %a, align 4
154 %or = or i64 %loada, 1229782942255909000 ; 0x11111111ffff8888
155 store i64 %or, i64 addrspace(1)* %out
159 ; SI-LABEL: {{^}}s_movk_i32_k11:
160 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x8fff{{$}}
161 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
162 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
163 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
164 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
166 define void @s_movk_i32_k11(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
167 %loada = load i64, i64 addrspace(1)* %a, align 4
168 %or = or i64 %loada, 1229782942255910911 ; 0x11111111ffff8fff
169 store i64 %or, i64 addrspace(1)* %out
173 ; SI-LABEL: {{^}}s_movk_i32_k12:
174 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff7001{{$}}
175 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
176 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
177 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
178 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
180 define void @s_movk_i32_k12(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
181 %loada = load i64, i64 addrspace(1)* %a, align 4
182 %or = or i64 %loada, 1229782942255902721 ; 0x11111111ffff7001
183 store i64 %or, i64 addrspace(1)* %out