1 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
3 ; In this test both the pointer and the offset operands to the
4 ; BUFFER_LOAD instructions end up being stored in vgprs. This
5 ; requires us to add the pointer and offset together, store the
6 ; result in the offset operand (vaddr), and then store 0 in an
7 ; sgpr register pair and use that for the pointer operand
8 ; (low 64-bits of srsrc).
10 ; CHECK-LABEL: {{^}}mubuf:
12 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
13 ; CHECK-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
15 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
17 ; CHECK: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
18 ; CHECK: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
19 define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
21 %0 = call i32 @llvm.r600.read.tidig.x() #1
22 %1 = call i32 @llvm.r600.read.tidig.y() #1
23 %2 = sext i32 %0 to i64
24 %3 = sext i32 %1 to i64
28 %4 = phi i64 [0, %entry], [%5, %loop]
30 %6 = getelementptr i8, i8 addrspace(1)* %in, i64 %5
31 %7 = load i8, i8 addrspace(1)* %6, align 1
33 %9 = getelementptr i8, i8 addrspace(1)* %in, i64 %8
34 %10 = load i8, i8 addrspace(1)* %9, align 1
36 %12 = sext i8 %11 to i32
37 store i32 %12, i32 addrspace(1)* %out
38 %13 = icmp slt i64 %5, 10
39 br i1 %13, label %loop, label %done
45 declare i32 @llvm.r600.read.tidig.x() #1
46 declare i32 @llvm.r600.read.tidig.y() #1
48 attributes #1 = { nounwind readnone }
50 ; Test moving an SMRD instruction to the VALU
52 ; CHECK-LABEL: {{^}}smrd_valu:
53 ; CHECK: buffer_load_dword [[OUT:v[0-9]+]]
54 ; CHECK: buffer_store_dword [[OUT]]
56 define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 addrspace(1)* %out) {
58 %0 = icmp ne i32 %a, 0
59 br i1 %0, label %if, label %else
62 %1 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
66 %2 = getelementptr i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
67 %3 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %2
71 %4 = phi i32 addrspace(2)* [%1, %if], [%3, %else]
72 %5 = getelementptr i32, i32 addrspace(2)* %4, i32 3000
73 %6 = load i32, i32 addrspace(2)* %5
74 store i32 %6, i32 addrspace(1)* %out
78 ; Test moving an SMRD with an immediate offset to the VALU
80 ; CHECK-LABEL: {{^}}smrd_valu2:
81 ; CHECK: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
82 define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) {
84 %0 = call i32 @llvm.r600.read.tidig.x() nounwind readnone
86 %2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %0, i32 4
87 %3 = load i32, i32 addrspace(2)* %2
88 store i32 %3, i32 addrspace(1)* %out
92 ; CHECK-LABEL: {{^}}smrd_valu2_max_smrd_offset:
93 ; CHECK: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
94 define void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) {
96 %0 = call i32 @llvm.r600.read.tidig.x() nounwind readnone
98 %2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %0, i32 255
99 %3 = load i32, i32 addrspace(2)* %2
100 store i32 %3, i32 addrspace(1)* %out
104 ; Offset is too big to fit in SMRD 8-bit offset, but small enough to
105 ; fit in MUBUF offset.
106 ; FIXME: We should be using the offset but we don't
108 ; CHECK-LABEL: {{^}}smrd_valu2_mubuf_offset:
109 ; CHECK: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
110 define void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) {
112 %0 = call i32 @llvm.r600.read.tidig.x() nounwind readnone
114 %2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %0, i32 256
115 %3 = load i32, i32 addrspace(2)* %2
116 store i32 %3, i32 addrspace(1)* %out
120 ; CHECK-LABEL: {{^}}s_load_imm_v8i32:
121 ; CHECK: buffer_load_dwordx4
122 ; CHECK: buffer_load_dwordx4
123 define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
125 %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
126 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
127 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
128 %tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
129 store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
133 ; CHECK-LABEL: {{^}}s_load_imm_v16i32:
134 ; CHECK: buffer_load_dwordx4
135 ; CHECK: buffer_load_dwordx4
136 ; CHECK: buffer_load_dwordx4
137 ; CHECK: buffer_load_dwordx4
138 define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
140 %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
141 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
142 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
143 %tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
144 store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32