1 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
2 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
4 ; This test checks that no VGPR to SGPR copies are created by the register
6 ; CHECK-LABEL: {{^}}phi1:
7 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
8 ; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]]
10 define void @phi1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
12 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
13 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1
14 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
15 %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
16 %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
17 %25 = fptosi float %23 to i32
18 %26 = icmp ne i32 %25, 0
19 br i1 %26, label %ENDIF, label %ELSE
21 ELSE: ; preds = %main_body
22 %27 = fsub float -0.000000e+00, %22
25 ENDIF: ; preds = %main_body, %ELSE
26 %temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ]
27 %28 = fadd float %temp.0, %24
28 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00)
32 ; Make sure this program doesn't crash
33 ; CHECK-LABEL: {{^}}phi2:
34 define void @phi2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
36 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
37 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1
38 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
39 %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
40 %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
41 %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
42 %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
43 %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
44 %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
45 %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
46 %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
47 %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
48 %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
49 %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
50 %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
51 %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
52 %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
53 %37 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0
54 %38 = load <32 x i8>, <32 x i8> addrspace(2)* %37, !tbaa !1
55 %39 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %1, i32 0
56 %40 = load <16 x i8>, <16 x i8> addrspace(2)* %39, !tbaa !1
57 %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
58 %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
59 %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
60 %44 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
61 %45 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
62 %46 = bitcast float %41 to i32
63 %47 = bitcast float %42 to i32
64 %48 = insertelement <2 x i32> undef, i32 %46, i32 0
65 %49 = insertelement <2 x i32> %48, i32 %47, i32 1
66 %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %38, <16 x i8> %40, i32 2)
67 %51 = extractelement <4 x float> %50, i32 2
68 %52 = call float @fabs(float %51)
69 %53 = fmul float %43, %43
70 %54 = fmul float %44, %44
71 %55 = fadd float %54, %53
72 %56 = fmul float %45, %45
73 %57 = fadd float %55, %56
74 %58 = call float @llvm.AMDGPU.rsq.f32(float %57)
75 %59 = fmul float %43, %58
76 %60 = fmul float %44, %58
77 %61 = fmul float %45, %58
78 %62 = fmul float %59, %23
79 %63 = fmul float %60, %24
80 %64 = fadd float %63, %62
81 %65 = fmul float %61, %25
82 %66 = fadd float %64, %65
83 %67 = fsub float -0.000000e+00, %26
84 %68 = fmul float %66, %52
85 %69 = fadd float %68, %67
86 %70 = fmul float %27, %69
87 %71 = fmul float %28, %69
88 %72 = call float @fabs(float %70)
89 %73 = fcmp olt float 0x3EE4F8B580000000, %72
90 %74 = sext i1 %73 to i32
91 %75 = bitcast i32 %74 to float
92 %76 = bitcast float %75 to i32
93 %77 = icmp ne i32 %76, 0
94 br i1 %77, label %IF, label %ENDIF
96 IF: ; preds = %main_body
97 %78 = fsub float -0.000000e+00, %70
98 %79 = call float @llvm.AMDIL.exp.(float %78)
99 %80 = fsub float -0.000000e+00, %79
100 %81 = fadd float 1.000000e+00, %80
101 %82 = fdiv float 1.000000e+00, %70
102 %83 = fmul float %81, %82
103 %84 = fmul float %32, %83
106 ENDIF: ; preds = %main_body, %IF
107 %temp4.0 = phi float [ %84, %IF ], [ %32, %main_body ]
108 %85 = call float @fabs(float %71)
109 %86 = fcmp olt float 0x3EE4F8B580000000, %85
110 %87 = sext i1 %86 to i32
111 %88 = bitcast i32 %87 to float
112 %89 = bitcast float %88 to i32
113 %90 = icmp ne i32 %89, 0
114 br i1 %90, label %IF25, label %ENDIF24
116 IF25: ; preds = %ENDIF
117 %91 = fsub float -0.000000e+00, %71
118 %92 = call float @llvm.AMDIL.exp.(float %91)
119 %93 = fsub float -0.000000e+00, %92
120 %94 = fadd float 1.000000e+00, %93
121 %95 = fdiv float 1.000000e+00, %71
122 %96 = fmul float %94, %95
123 %97 = fmul float %36, %96
126 ENDIF24: ; preds = %ENDIF, %IF25
127 %temp8.0 = phi float [ %97, %IF25 ], [ %36, %ENDIF ]
128 %98 = fmul float %29, %temp4.0
129 %99 = fmul float %30, %temp4.0
130 %100 = fmul float %31, %temp4.0
131 %101 = fmul float %33, %temp8.0
132 %102 = fadd float %101, %98
133 %103 = fmul float %34, %temp8.0
134 %104 = fadd float %103, %99
135 %105 = fmul float %35, %temp8.0
136 %106 = fadd float %105, %100
137 %107 = call float @llvm.pow.f32(float %52, float %22)
138 %108 = fsub float -0.000000e+00, %102
139 %109 = fmul float %108, %107
140 %110 = fsub float -0.000000e+00, %104
141 %111 = fmul float %110, %107
142 %112 = fsub float -0.000000e+00, %106
143 %113 = fmul float %112, %107
144 %114 = call i32 @llvm.SI.packf16(float %109, float %111)
145 %115 = bitcast i32 %114 to float
146 %116 = call i32 @llvm.SI.packf16(float %113, float 1.000000e+00)
147 %117 = bitcast i32 %116 to float
148 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %115, float %117, float %115, float %117)
152 ; We just want ot make sure the program doesn't crash
153 ; CHECK-LABEL: {{^}}loop:
155 define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
157 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
158 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1
159 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
160 %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
161 %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
162 %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
163 %26 = fptosi float %25 to i32
164 %27 = bitcast i32 %26 to float
165 %28 = bitcast float %27 to i32
168 LOOP: ; preds = %ENDIF, %main_body
169 %temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ]
170 %temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ]
171 %temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ]
172 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ]
173 %29 = bitcast float %temp8.0 to i32
174 %30 = icmp sge i32 %29, %28
175 %31 = sext i1 %30 to i32
176 %32 = bitcast i32 %31 to float
177 %33 = bitcast float %32 to i32
178 %34 = icmp ne i32 %33, 0
179 br i1 %34, label %IF, label %ENDIF
182 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00)
185 ENDIF: ; preds = %LOOP
186 %35 = bitcast float %temp8.0 to i32
188 %37 = bitcast i32 %36 to float
192 ; Function Attrs: nounwind readnone
193 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
195 ; Function Attrs: readonly
196 declare float @fabs(float) #2
198 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
200 attributes #0 = { "ShaderType"="0" }
201 attributes #1 = { nounwind readnone }
202 attributes #2 = { readonly }
203 attributes #3 = { readnone }
204 attributes #4 = { nounwind readonly }
206 !0 = !{!"const", null}
207 !1 = !{!0, !0, i64 0, i32 1}
209 ; Function Attrs: nounwind readnone
210 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
212 ; Function Attrs: nounwind readnone
213 declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
215 ; Function Attrs: readnone
216 declare float @llvm.AMDGPU.rsq.f32(float) #3
218 ; Function Attrs: readnone
219 declare float @llvm.AMDIL.exp.(float) #3
221 ; Function Attrs: nounwind readonly
222 declare float @llvm.pow.f32(float, float) #4
224 ; Function Attrs: nounwind readnone
225 declare i32 @llvm.SI.packf16(float, float) #1
227 ; This checks for a bug in the FixSGPRCopies pass where VReg96
228 ; registers were being identified as an SGPR regclass which was causing
229 ; an assertion failure.
231 ; CHECK-LABEL: {{^}}sample_v3:
232 ; CHECK: image_sample
233 ; CHECK: image_sample
236 define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
239 %21 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
240 %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, !tbaa !2
241 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
242 %24 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
243 %25 = load <32 x i8>, <32 x i8> addrspace(2)* %24, !tbaa !2
244 %26 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
245 %27 = load <16 x i8>, <16 x i8> addrspace(2)* %26, !tbaa !2
246 %28 = fcmp oeq float %23, 0.0
247 br i1 %28, label %if, label %else
250 %val.if = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 0, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
251 %val.if.0 = extractelement <4 x float> %val.if, i32 0
252 %val.if.1 = extractelement <4 x float> %val.if, i32 1
253 %val.if.2 = extractelement <4 x float> %val.if, i32 2
257 %val.else = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 1, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
258 %val.else.0 = extractelement <4 x float> %val.else, i32 0
259 %val.else.1 = extractelement <4 x float> %val.else, i32 1
260 %val.else.2 = extractelement <4 x float> %val.else, i32 2
264 %val.0 = phi float [%val.if.0, %if], [%val.else.0, %else]
265 %val.1 = phi float [%val.if.1, %if], [%val.else.1, %else]
266 %val.2 = phi float [%val.if.2, %if], [%val.else.2, %else]
267 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.0)
271 !2 = !{!"const", null, i32 1}
273 ; CHECK-LABEL: {{^}}copy1:
274 ; CHECK: buffer_load_dword
277 define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) {
279 %0 = load float, float addrspace(1)* %in0
280 %1 = fcmp oeq float %0, 0.0
281 br i1 %1, label %if0, label %endif
284 %2 = bitcast float %0 to i32
285 %3 = fcmp olt float %0, 0.0
286 br i1 %3, label %if1, label %endif
293 %5 = phi i32 [ 0, %entry ], [ %2, %if0 ], [ %4, %if1 ]
294 %6 = bitcast i32 %5 to float
295 store float %6, float addrspace(1)* %out
299 ; This test is just checking that we don't crash / assertion fail.
300 ; CHECK-LABEL: {{^}}copy2:
303 define void @copy2([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
308 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
309 %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
310 %g = icmp eq i32 0, %t
311 %l = bitcast float %temp4.7 to i32
312 br i1 %g, label %IF70, label %ENDIF69
315 %q = icmp ne i32 %l, 13
316 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00
317 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
322 %v = bitcast i32 %u to float
327 attributes #0 = { "ShaderType"="0" }
329 ; This test checks that image_sample resource descriptors aren't loaded into
330 ; vgprs. The verifier will fail if this happens.
331 ; CHECK-LABEL:{{^}}sample_rsrc:
332 ; CHECK: image_sample
333 ; CHECK: image_sample
335 define void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
337 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0
338 %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
339 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16)
340 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0
341 %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !0
342 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0
343 %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !0
344 %tmp29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg7)
345 %tmp30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg7)
346 %tmp31 = bitcast float %tmp23 to i32
347 %tmp36 = icmp ne i32 %tmp31, 0
348 br i1 %tmp36, label %bb38, label %bb80
351 %tmp52 = bitcast float %tmp29 to i32
352 %tmp53 = bitcast float %tmp30 to i32
353 %tmp54 = insertelement <2 x i32> undef, i32 %tmp52, i32 0
354 %tmp55 = insertelement <2 x i32> %tmp54, i32 %tmp53, i32 1
355 %tmp56 = bitcast <8 x i32> %tmp26 to <32 x i8>
356 %tmp57 = bitcast <4 x i32> %tmp28 to <16 x i8>
357 %tmp58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %tmp55, <32 x i8> %tmp56, <16 x i8> %tmp57, i32 2)
361 %tmp81 = bitcast float %tmp29 to i32
362 %tmp82 = bitcast float %tmp30 to i32
363 %tmp82.2 = add i32 %tmp82, 1
364 %tmp83 = insertelement <2 x i32> undef, i32 %tmp81, i32 0
365 %tmp84 = insertelement <2 x i32> %tmp83, i32 %tmp82.2, i32 1
366 %tmp85 = bitcast <8 x i32> %tmp26 to <32 x i8>
367 %tmp86 = bitcast <4 x i32> %tmp28 to <16 x i8>
368 %tmp87 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %tmp84, <32 x i8> %tmp85, <16 x i8> %tmp86, i32 2)
371 bb71: ; preds = %bb80, %bb38
372 %tmp72 = phi <4 x float> [ %tmp58, %bb38 ], [ %tmp87, %bb80 ]
373 %tmp88 = extractelement <4 x float> %tmp72, i32 0
374 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp88, float %tmp88, float %tmp88, float %tmp88)
378 attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
379 attributes #1 = { nounwind readnone }