1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
2 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s
5 ;EG-LABEL: {{^}}ashr_v2i32:
6 ;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7 ;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
9 ;SI-LABEL: {{^}}ashr_v2i32:
10 ;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
11 ;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
13 ;VI-LABEL: {{^}}ashr_v2i32:
14 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
15 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
17 define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
18 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
19 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
20 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
21 %result = ashr <2 x i32> %a, %b
22 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
26 ;EG-LABEL: {{^}}ashr_v4i32:
27 ;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
30 ;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
32 ;SI-LABEL: {{^}}ashr_v4i32:
33 ;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
34 ;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
35 ;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
36 ;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
38 ;VI-LABEL: {{^}}ashr_v4i32:
39 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
40 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
41 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
42 ;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44 define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
45 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
46 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
47 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
48 %result = ashr <4 x i32> %a, %b
49 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
53 ;EG-LABEL: {{^}}ashr_i64:
56 ;SI-LABEL: {{^}}ashr_i64:
57 ;SI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
59 ;VI-LABEL: {{^}}ashr_i64:
60 ;VI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
62 define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) {
64 %0 = sext i32 %in to i64
66 store i64 %1, i64 addrspace(1)* %out
70 ;EG-LABEL: {{^}}ashr_i64_2:
71 ;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
72 ;EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
73 ;EG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
74 ;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
75 ;EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
76 ;EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
77 ;EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
78 ;EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
79 ;EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
80 ;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
81 ;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
82 ;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
84 ;SI-LABEL: {{^}}ashr_i64_2:
85 ;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ;VI-LABEL: {{^}}ashr_i64_2:
88 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
90 define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
92 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
93 %a = load i64, i64 addrspace(1) * %in
94 %b = load i64, i64 addrspace(1) * %b_ptr
95 %result = ashr i64 %a, %b
96 store i64 %result, i64 addrspace(1)* %out
100 ;EG-LABEL: {{^}}ashr_v2i64:
101 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
102 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
103 ;EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
104 ;EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
105 ;EG-DAG: LSHL {{.*}}, 1
106 ;EG-DAG: LSHL {{.*}}, 1
107 ;EG-DAG: ASHR {{.*}}, [[SHA]]
108 ;EG-DAG: ASHR {{.*}}, [[SHB]]
109 ;EG-DAG: LSHR {{.*}}, [[SHA]]
110 ;EG-DAG: LSHR {{.*}}, [[SHB]]
113 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
114 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
117 ;EG-DAG: ASHR {{.*}}, literal
118 ;EG-DAG: ASHR {{.*}}, literal
119 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
120 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
126 ;SI-LABEL: {{^}}ashr_v2i64:
127 ;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
130 ;VI-LABEL: {{^}}ashr_v2i64:
131 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
132 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
134 define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
135 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
136 %a = load <2 x i64>, <2 x i64> addrspace(1) * %in
137 %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
138 %result = ashr <2 x i64> %a, %b
139 store <2 x i64> %result, <2 x i64> addrspace(1)* %out
143 ;EG-LABEL: {{^}}ashr_v4i64:
144 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
145 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
146 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
147 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
148 ;EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
149 ;EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
150 ;EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
151 ;EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
152 ;EG-DAG: LSHL {{.*}}, 1
153 ;EG-DAG: LSHL {{.*}}, 1
154 ;EG-DAG: LSHL {{.*}}, 1
155 ;EG-DAG: LSHL {{.*}}, 1
156 ;EG-DAG: ASHR {{.*}}, [[SHA]]
157 ;EG-DAG: ASHR {{.*}}, [[SHB]]
158 ;EG-DAG: ASHR {{.*}}, [[SHC]]
159 ;EG-DAG: ASHR {{.*}}, [[SHD]]
160 ;EG-DAG: LSHR {{.*}}, [[SHA]]
161 ;EG-DAG: LSHR {{.*}}, [[SHB]]
162 ;EG-DAG: LSHR {{.*}}, [[SHA]]
163 ;EG-DAG: LSHR {{.*}}, [[SHB]]
168 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
169 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
170 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
171 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
176 ;EG-DAG: ASHR {{.*}}, literal
177 ;EG-DAG: ASHR {{.*}}, literal
178 ;EG-DAG: ASHR {{.*}}, literal
179 ;EG-DAG: ASHR {{.*}}, literal
180 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
181 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
182 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
183 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
193 ;SI-LABEL: {{^}}ashr_v4i64:
194 ;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
195 ;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
196 ;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
197 ;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
199 ;VI-LABEL: {{^}}ashr_v4i64:
200 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
201 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
202 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
203 ;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
205 define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
206 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
207 %a = load <4 x i64>, <4 x i64> addrspace(1) * %in
208 %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
209 %result = ashr <4 x i64> %a, %b
210 store <4 x i64> %result, <4 x i64> addrspace(1)* %out