1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
6 ;===------------------------------------------------------------------------===;
8 ;===------------------------------------------------------------------------===;
9 ; FUNC-LABEL: {{^}}store_i1:
11 ; SI: buffer_store_byte
12 define void @store_i1(i1 addrspace(1)* %out) {
14 store i1 true, i1 addrspace(1)* %out
19 ; FUNC-LABEL: {{^}}store_i8:
20 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
22 ; IG 0: Get the byte index and truncate the value
23 ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
24 ; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
25 ; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
26 ; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)
29 ; IG 1: Truncate the calculated the shift amount for the mask
31 ; IG 2: Shift the value and the mask
32 ; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
33 ; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
35 ; IG 3: Initialize the Y and Z channels to zero
36 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
37 ; EG: MOV T[[RW_GPR]].Y, 0.0
38 ; EG: MOV * T[[RW_GPR]].Z, 0.0
40 ; SI: buffer_store_byte
42 define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
44 store i8 %in, i8 addrspace(1)* %out
49 ; FUNC-LABEL: {{^}}store_i16:
50 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
52 ; IG 0: Get the byte index and truncate the value
55 ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
56 ; EG-NEXT: 3(4.203895e-45),
58 ; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
59 ; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
61 ; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
62 ; IG 1: Truncate the calculated the shift amount for the mask
64 ; IG 2: Shift the value and the mask
65 ; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
66 ; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
68 ; IG 3: Initialize the Y and Z channels to zero
69 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
70 ; EG: MOV T[[RW_GPR]].Y, 0.0
71 ; EG: MOV * T[[RW_GPR]].Z, 0.0
73 ; SI: buffer_store_short
74 define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
76 store i16 %in, i16 addrspace(1)* %out
80 ; FUNC-LABEL: {{^}}store_v2i8:
82 ; EG-NOT: MEM_RAT MSKOR
84 ; SI: buffer_store_byte
85 ; SI: buffer_store_byte
86 define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
88 %0 = trunc <2 x i32> %in to <2 x i8>
89 store <2 x i8> %0, <2 x i8> addrspace(1)* %out
94 ; FUNC-LABEL: {{^}}store_v2i16:
95 ; EG: MEM_RAT_CACHELESS STORE_RAW
97 ; CM: MEM_RAT_CACHELESS STORE_DWORD
99 ; SI: buffer_store_short
100 ; SI: buffer_store_short
101 define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
103 %0 = trunc <2 x i32> %in to <2 x i16>
104 store <2 x i16> %0, <2 x i16> addrspace(1)* %out
108 ; FUNC-LABEL: {{^}}store_v4i8:
109 ; EG: MEM_RAT_CACHELESS STORE_RAW
111 ; CM: MEM_RAT_CACHELESS STORE_DWORD
113 ; SI: buffer_store_byte
114 ; SI: buffer_store_byte
115 ; SI: buffer_store_byte
116 ; SI: buffer_store_byte
117 define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
119 %0 = trunc <4 x i32> %in to <4 x i8>
120 store <4 x i8> %0, <4 x i8> addrspace(1)* %out
124 ; floating-point store
125 ; FUNC-LABEL: {{^}}store_f32:
126 ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
128 ; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
130 ; SI: buffer_store_dword
132 define void @store_f32(float addrspace(1)* %out, float %in) {
133 store float %in, float addrspace(1)* %out
137 ; FUNC-LABEL: {{^}}store_v4i16:
142 ; EG-NOT: MEM_RAT MSKOR
144 ; SI: buffer_store_short
145 ; SI: buffer_store_short
146 ; SI: buffer_store_short
147 ; SI: buffer_store_short
148 ; SI-NOT: buffer_store_byte
149 define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
151 %0 = trunc <4 x i32> %in to <4 x i16>
152 store <4 x i16> %0, <4 x i16> addrspace(1)* %out
156 ; vec2 floating-point stores
157 ; FUNC-LABEL: {{^}}store_v2f32:
158 ; EG: MEM_RAT_CACHELESS STORE_RAW
160 ; CM: MEM_RAT_CACHELESS STORE_DWORD
162 ; SI: buffer_store_dwordx2
164 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
166 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
167 %1 = insertelement <2 x float> %0, float %b, i32 1
168 store <2 x float> %1, <2 x float> addrspace(1)* %out
172 ; FUNC-LABEL: {{^}}store_v4i32:
173 ; EG: MEM_RAT_CACHELESS STORE_RAW
174 ; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
176 ; CM: MEM_RAT_CACHELESS STORE_DWORD
177 ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
179 ; SI: buffer_store_dwordx4
180 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
182 store <4 x i32> %in, <4 x i32> addrspace(1)* %out
186 ; FUNC-LABEL: {{^}}store_i64_i8:
188 ; SI: buffer_store_byte
189 define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) {
191 %0 = trunc i64 %in to i8
192 store i8 %0, i8 addrspace(1)* %out
196 ; FUNC-LABEL: {{^}}store_i64_i16:
198 ; SI: buffer_store_short
199 define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) {
201 %0 = trunc i64 %in to i16
202 store i16 %0, i16 addrspace(1)* %out
206 ;===------------------------------------------------------------------------===;
207 ; Local Address Space
208 ;===------------------------------------------------------------------------===;
210 ; FUNC-LABEL: {{^}}store_local_i1:
213 define void @store_local_i1(i1 addrspace(3)* %out) {
215 store i1 true, i1 addrspace(3)* %out
219 ; FUNC-LABEL: {{^}}store_local_i8:
223 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
224 store i8 %in, i8 addrspace(3)* %out
228 ; FUNC-LABEL: {{^}}store_local_i16:
229 ; EG: LDS_SHORT_WRITE
232 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
233 store i16 %in, i16 addrspace(3)* %out
237 ; FUNC-LABEL: {{^}}store_local_v2i16:
244 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
246 store <2 x i16> %in, <2 x i16> addrspace(3)* %out
250 ; FUNC-LABEL: {{^}}store_local_v4i8:
259 define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) {
261 store <4 x i8> %in, <4 x i8> addrspace(3)* %out
265 ; FUNC-LABEL: {{^}}store_local_v2i32:
273 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
275 store <2 x i32> %in, <2 x i32> addrspace(3)* %out
279 ; FUNC-LABEL: {{^}}store_local_v4i32:
292 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
294 store <4 x i32> %in, <4 x i32> addrspace(3)* %out
298 ; FUNC-LABEL: {{^}}store_local_v4i32_align4:
311 define void @store_local_v4i32_align4(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
313 store <4 x i32> %in, <4 x i32> addrspace(3)* %out, align 4
317 ; FUNC-LABEL: {{^}}store_local_i64_i8:
320 define void @store_local_i64_i8(i8 addrspace(3)* %out, i64 %in) {
322 %0 = trunc i64 %in to i8
323 store i8 %0, i8 addrspace(3)* %out
327 ; FUNC-LABEL: {{^}}store_local_i64_i16:
328 ; EG: LDS_SHORT_WRITE
330 define void @store_local_i64_i16(i16 addrspace(3)* %out, i64 %in) {
332 %0 = trunc i64 %in to i16
333 store i16 %0, i16 addrspace(3)* %out
337 ; The stores in this function are combined by the optimizer to create a
338 ; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
339 ; should not try to split the 64-bit store back into 2 32-bit stores.
341 ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
342 ; be two 32-bit stores.
344 ; FUNC-LABEL: {{^}}vecload2:
345 ; EG: MEM_RAT_CACHELESS STORE_RAW
347 ; CM: MEM_RAT_CACHELESS STORE_DWORD
349 ; SI: buffer_store_dwordx2
350 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
352 %0 = load i32, i32 addrspace(2)* %mem, align 4
353 %arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1
354 %1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4
355 store i32 %0, i32 addrspace(1)* %out, align 4
356 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
357 store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
361 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
363 ; When i128 was a legal type this program generated cannot select errors:
365 ; FUNC-LABEL: {{^}}"i128-const-store":
366 ; FIXME: We should be able to to this with one store instruction
375 ; SI: buffer_store_dwordx4
376 define void @i128-const-store(i32 addrspace(1)* %out) {
378 store i32 1, i32 addrspace(1)* %out, align 4
379 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
380 store i32 1, i32 addrspace(1)* %arrayidx2, align 4
381 %arrayidx4 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 2
382 store i32 2, i32 addrspace(1)* %arrayidx4, align 4
383 %arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 3
384 store i32 2, i32 addrspace(1)* %arrayidx6, align 4