1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -o - %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s
4 ; SI-LABEL:{{^}}row_filter_C1_D0:
6 ; Function Attrs: nounwind
7 define void @row_filter_C1_D0() {
9 br i1 undef, label %for.inc.1, label %do.body.preheader
11 do.body.preheader: ; preds = %entry
12 %0 = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1
13 br i1 undef, label %do.body56.1, label %do.body90
15 do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader
16 %1 = phi <4 x i32> [ %6, %do.body56.2 ], [ %5, %do.body56.1 ], [ %0, %do.body.preheader ]
17 %2 = insertelement <4 x i32> %1, i32 undef, i32 2
18 %3 = insertelement <4 x i32> %2, i32 undef, i32 3
19 br i1 undef, label %do.body124.1, label %do.body.1562.preheader
21 do.body.1562.preheader: ; preds = %do.body124.1, %do.body90
22 %storemerge = phi <4 x i32> [ %3, %do.body90 ], [ %7, %do.body124.1 ]
23 %4 = insertelement <4 x i32> undef, i32 undef, i32 1
26 do.body56.1: ; preds = %do.body.preheader
27 %5 = insertelement <4 x i32> %0, i32 undef, i32 1
28 %or.cond472.1 = or i1 undef, undef
29 br i1 %or.cond472.1, label %do.body56.2, label %do.body90
31 do.body56.2: ; preds = %do.body56.1
32 %6 = insertelement <4 x i32> %5, i32 undef, i32 1
35 do.body124.1: ; preds = %do.body90
36 %7 = insertelement <4 x i32> %3, i32 undef, i32 3
37 br label %do.body.1562.preheader
39 for.inc.1: ; preds = %do.body.1562.preheader, %entry
40 %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, %do.body.1562.preheader ]
41 %add.i495 = add <4 x i32> %storemerge591, undef
47 define void @foo() #0 {
49 br i1 undef, label %bb2, label %bb1
52 br i1 undef, label %bb4, label %bb6
54 bb2: ; preds = %bb4, %bb
55 %tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ]
56 br i1 undef, label %bb9, label %bb13
58 bb4: ; preds = %bb7, %bb6, %bb1
59 %tmp5 = phi float [ undef, %bb1 ], [ undef, %bb6 ], [ %tmp8, %bb7 ]
63 br i1 undef, label %bb7, label %bb4
66 %tmp8 = fmul float undef, undef
70 %tmp10 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 2)
71 %tmp11 = extractelement <4 x float> %tmp10, i32 1
72 %tmp12 = extractelement <4 x float> %tmp10, i32 3
76 br i1 undef, label %bb23, label %bb24
78 bb14: ; preds = %bb27, %bb24, %bb9
79 %tmp15 = phi float [ %tmp12, %bb9 ], [ undef, %bb27 ], [ 0.000000e+00, %bb24 ]
80 %tmp16 = phi float [ %tmp11, %bb9 ], [ undef, %bb27 ], [ %tmp25, %bb24 ]
81 %tmp17 = fmul float 10.5, %tmp16
82 %tmp18 = fmul float 11.5, %tmp15
83 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp18, float %tmp17, float %tmp17, float %tmp17)
87 br i1 undef, label %bb24, label %bb26
89 bb24: ; preds = %bb26, %bb23, %bb13
90 %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ]
91 br i1 undef, label %bb27, label %bb14
100 ; Function Attrs: nounwind readnone
101 declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
103 ; Function Attrs: nounwind readnone
104 declare i32 @llvm.SI.packf16(float, float) #1
106 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
108 attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" }
109 attributes #1 = { nounwind readnone }