1 ; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs
2 target triple = "arm-pc-linux-gnu"
4 ; This test case would accidentally use the same physreg for two virtregs
5 ; because allocVirtReg forgot to check if registers were already used in the
7 ; This caused the RegScavenger to complain, but -verify-machineinstrs also
10 %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
12 @search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1]
13 @bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1]
15 declare fastcc i32 @FirstOne()
17 define fastcc void @Evaluate() {
19 br i1 false, label %cond_false186, label %cond_true
21 cond_true: ; preds = %entry
24 cond_false186: ; preds = %entry
25 br i1 false, label %cond_true293, label %bb203
27 bb203: ; preds = %cond_false186
30 cond_true293: ; preds = %cond_false186
31 br i1 false, label %cond_true298, label %cond_next317
33 cond_true298: ; preds = %cond_true293
34 br i1 false, label %cond_next518, label %cond_true397.preheader
36 cond_next317: ; preds = %cond_true293
39 cond_true397.preheader: ; preds = %cond_true298
42 cond_next518: ; preds = %cond_true298
43 br i1 false, label %bb1069, label %cond_true522
45 cond_true522: ; preds = %cond_next518
48 bb1069: ; preds = %cond_next518
49 br i1 false, label %cond_next1131, label %bb1096
51 bb1096: ; preds = %bb1069
54 cond_next1131: ; preds = %bb1069
55 br i1 false, label %cond_next1207, label %cond_true1150
57 cond_true1150: ; preds = %cond_next1131
60 cond_next1207: ; preds = %cond_next1131
61 br i1 false, label %cond_next1219, label %cond_true1211
63 cond_true1211: ; preds = %cond_next1207
66 cond_next1219: ; preds = %cond_next1207
67 br i1 false, label %cond_true1223, label %cond_next1283
69 cond_true1223: ; preds = %cond_next1219
70 br i1 false, label %cond_true1254, label %cond_true1264
72 cond_true1254: ; preds = %cond_true1223
73 br i1 false, label %bb1567, label %cond_true1369.preheader
75 cond_true1264: ; preds = %cond_true1223
78 cond_next1283: ; preds = %cond_next1219
81 cond_true1369.preheader: ; preds = %cond_true1254
84 bb1567: ; preds = %cond_true1254
85 %tmp1591 = load i64, i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1]
86 %tmp1572 = tail call fastcc i32 @FirstOne() ; <i32> [#uses=1]
87 %tmp1594 = load i32, i32* undef ; <i32> [#uses=1]
88 %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; <i8> [#uses=1]
89 %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1]
90 %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1]
91 %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1]
92 %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1]
93 %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1]
94 %tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1]
95 %tmp1599 = load i32, i32* %tmp1598 ; <i32> [#uses=1]
96 %tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1]
97 br i1 undef, label %cond_next1637, label %cond_true1607
99 cond_true1607: ; preds = %bb1567
102 cond_next1637: ; preds = %bb1567
103 %tmp1662 = sub i32 %tmp1602, 0 ; <i32> [#uses=0]