1 ; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
2 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
3 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
4 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
5 ; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
7 define void @func(i32 %argc, i8** %argv) nounwind {
9 %argc.addr = alloca i32 ; <i32*> [#uses=1]
10 %argv.addr = alloca i8** ; <i8***> [#uses=1]
11 %val1 = alloca i32 ; <i32*> [#uses=2]
12 %val2 = alloca i32 ; <i32*> [#uses=15]
13 %andt = alloca i32 ; <i32*> [#uses=2]
14 %ort = alloca i32 ; <i32*> [#uses=2]
15 %xort = alloca i32 ; <i32*> [#uses=2]
16 %old = alloca i32 ; <i32*> [#uses=18]
17 %temp = alloca i32 ; <i32*> [#uses=2]
18 store i32 %argc, i32* %argc.addr
19 store i8** %argv, i8*** %argv.addr
20 store i32 0, i32* %val1
21 store i32 31, i32* %val2
22 store i32 3855, i32* %andt
23 store i32 3855, i32* %ort
24 store i32 3855, i32* %xort
25 store i32 4, i32* %temp
26 %tmp = load i32* %temp
30 ; CHECK-T1: blx ___sync_fetch_and_add_4
31 ; CHECK-M0: bl ___sync_fetch_and_add_4
32 ; CHECK-BAREMETAL: add
33 ; CHECK-BAREMETAL-NOT: __sync
34 %0 = atomicrmw add i32* %val1, i32 %tmp monotonic
35 store i32 %0, i32* %old
39 ; CHECK-T1: blx ___sync_fetch_and_sub_4
40 ; CHECK-M0: bl ___sync_fetch_and_sub_4
41 ; CHECK-BAREMETAL: sub
42 ; CHECK-BAREMETAL-NOT: __sync
43 %1 = atomicrmw sub i32* %val2, i32 30 monotonic
44 store i32 %1, i32* %old
48 ; CHECK-T1: blx ___sync_fetch_and_add_4
49 ; CHECK-M0: bl ___sync_fetch_and_add_4
50 ; CHECK-BAREMETAL: add
51 ; CHECK-BAREMETAL-NOT: __sync
52 %2 = atomicrmw add i32* %val2, i32 1 monotonic
53 store i32 %2, i32* %old
57 ; CHECK-T1: blx ___sync_fetch_and_sub_4
58 ; CHECK-M0: bl ___sync_fetch_and_sub_4
59 ; CHECK-BAREMETAL: sub
60 ; CHECK-BAREMETAL-NOT: __sync
61 %3 = atomicrmw sub i32* %val2, i32 1 monotonic
62 store i32 %3, i32* %old
66 ; CHECK-T1: blx ___sync_fetch_and_and_4
67 ; CHECK-M0: bl ___sync_fetch_and_and_4
68 ; CHECK-BAREMETAL: and
69 ; CHECK-BAREMETAL-NOT: __sync
70 %4 = atomicrmw and i32* %andt, i32 4080 monotonic
71 store i32 %4, i32* %old
75 ; CHECK-T1: blx ___sync_fetch_and_or_4
76 ; CHECK-M0: bl ___sync_fetch_and_or_4
78 ; CHECK-BAREMETAL-NOT: __sync
79 %5 = atomicrmw or i32* %ort, i32 4080 monotonic
80 store i32 %5, i32* %old
84 ; CHECK-T1: blx ___sync_fetch_and_xor_4
85 ; CHECK-M0: bl ___sync_fetch_and_xor_4
86 ; CHECK-BAREMETAL: eor
87 ; CHECK-BAREMETAL-NOT: __sync
88 %6 = atomicrmw xor i32* %xort, i32 4080 monotonic
89 store i32 %6, i32* %old
93 ; CHECK-T1: blx ___sync_fetch_and_min_4
94 ; CHECK-M0: bl ___sync_fetch_and_min_4
95 ; CHECK-BAREMETAL: cmp
96 ; CHECK-BAREMETAL-NOT: __sync
97 %7 = atomicrmw min i32* %val2, i32 16 monotonic
98 store i32 %7, i32* %old
103 ; CHECK-T1: blx ___sync_fetch_and_min_4
104 ; CHECK-M0: bl ___sync_fetch_and_min_4
105 ; CHECK-BAREMETAL: cmp
106 ; CHECK-BAREMETAL-NOT: __sync
107 %8 = atomicrmw min i32* %val2, i32 %neg monotonic
108 store i32 %8, i32* %old
112 ; CHECK-T1: blx ___sync_fetch_and_max_4
113 ; CHECK-M0: bl ___sync_fetch_and_max_4
114 ; CHECK-BAREMETAL: cmp
115 ; CHECK-BAREMETAL-NOT: __sync
116 %9 = atomicrmw max i32* %val2, i32 1 monotonic
117 store i32 %9, i32* %old
121 ; CHECK-T1: blx ___sync_fetch_and_max_4
122 ; CHECK-M0: bl ___sync_fetch_and_max_4
123 ; CHECK-BAREMETAL: cmp
124 ; CHECK-BAREMETAL-NOT: __sync
125 %10 = atomicrmw max i32* %val2, i32 0 monotonic
126 store i32 %10, i32* %old
130 ; CHECK-T1: blx ___sync_fetch_and_umin_4
131 ; CHECK-M0: bl ___sync_fetch_and_umin_4
132 ; CHECK-BAREMETAL: cmp
133 ; CHECK-BAREMETAL-NOT: __sync
134 %11 = atomicrmw umin i32* %val2, i32 16 monotonic
135 store i32 %11, i32* %old
140 ; CHECK-T1: blx ___sync_fetch_and_umin_4
141 ; CHECK-M0: bl ___sync_fetch_and_umin_4
142 ; CHECK-BAREMETAL: cmp
143 ; CHECK-BAREMETAL-NOT: __sync
144 %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
145 store i32 %12, i32* %old
149 ; CHECK-T1: blx ___sync_fetch_and_umax_4
150 ; CHECK-M0: bl ___sync_fetch_and_umax_4
151 ; CHECK-BAREMETAL: cmp
152 ; CHECK-BAREMETAL-NOT: __sync
153 %13 = atomicrmw umax i32* %val2, i32 1 monotonic
154 store i32 %13, i32* %old
158 ; CHECK-T1: blx ___sync_fetch_and_umax_4
159 ; CHECK-M0: bl ___sync_fetch_and_umax_4
160 ; CHECK-BAREMETAL: cmp
161 ; CHECK-BAREMETAL-NOT: __sync
162 %14 = atomicrmw umax i32* %val2, i32 0 monotonic
163 store i32 %14, i32* %old
168 define void @func2() nounwind {
172 store i16 31, i16* %val
176 ; CHECK-T1: blx ___sync_fetch_and_umin_2
177 ; CHECK-M0: bl ___sync_fetch_and_umin_2
178 ; CHECK-BAREMETAL: cmp
179 ; CHECK-BAREMETAL-NOT: __sync
180 %0 = atomicrmw umin i16* %val, i16 16 monotonic
181 store i16 %0, i16* %old
186 ; CHECK-T1: blx ___sync_fetch_and_umin_2
187 ; CHECK-M0: bl ___sync_fetch_and_umin_2
188 ; CHECK-BAREMETAL: cmp
189 ; CHECK-BAREMETAL-NOT: __sync
190 %1 = atomicrmw umin i16* %val, i16 %uneg monotonic
191 store i16 %1, i16* %old
195 ; CHECK-T1: blx ___sync_fetch_and_umax_2
196 ; CHECK-M0: bl ___sync_fetch_and_umax_2
197 ; CHECK-BAREMETAL: cmp
198 ; CHECK-BAREMETAL-NOT: __sync
199 %2 = atomicrmw umax i16* %val, i16 1 monotonic
200 store i16 %2, i16* %old
204 ; CHECK-T1: blx ___sync_fetch_and_umax_2
205 ; CHECK-M0: bl ___sync_fetch_and_umax_2
206 ; CHECK-BAREMETAL: cmp
207 ; CHECK-BAREMETAL-NOT: __sync
208 %3 = atomicrmw umax i16* %val, i16 0 monotonic
209 store i16 %3, i16* %old
213 define void @func3() nounwind {
217 store i8 31, i8* %val
221 ; CHECK-T1: blx ___sync_fetch_and_umin_1
222 ; CHECK-M0: bl ___sync_fetch_and_umin_1
223 ; CHECK-BAREMETAL: cmp
224 ; CHECK-BAREMETAL-NOT: __sync
225 %0 = atomicrmw umin i8* %val, i8 16 monotonic
226 store i8 %0, i8* %old
230 ; CHECK-T1: blx ___sync_fetch_and_umin_1
231 ; CHECK-M0: bl ___sync_fetch_and_umin_1
232 ; CHECK-BAREMETAL: cmp
233 ; CHECK-BAREMETAL-NOT: __sync
235 %1 = atomicrmw umin i8* %val, i8 %uneg monotonic
236 store i8 %1, i8* %old
240 ; CHECK-T1: blx ___sync_fetch_and_umax_1
241 ; CHECK-M0: bl ___sync_fetch_and_umax_1
242 ; CHECK-BAREMETAL: cmp
243 ; CHECK-BAREMETAL-NOT: __sync
244 %2 = atomicrmw umax i8* %val, i8 1 monotonic
245 store i8 %2, i8* %old
249 ; CHECK-T1: blx ___sync_fetch_and_umax_1
250 ; CHECK-M0: bl ___sync_fetch_and_umax_1
251 ; CHECK-BAREMETAL: cmp
252 ; CHECK-BAREMETAL-NOT: __sync
253 %3 = atomicrmw umax i8* %val, i8 0 monotonic
254 store i8 %3, i8* %old
259 ; This function should not need to use callee-saved registers.
260 ; rdar://problem/12203728
262 define i32 @func4(i32* %p) nounwind optsize ssp {
264 %0 = atomicrmw add i32* %p, i32 1 monotonic
268 define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
269 ; CHECK-LABEL: test_cmpxchg_fail_order:
271 %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
272 %oldval = extractvalue { i32, i1 } %pair, 0
274 ; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
275 ; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
276 ; CHECK: cmp [[OLDVAL]], r1
278 ; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
279 ; CHECK: cmp [[SUCCESS]], #0
280 ; CHECK: bne [[LOOP_BB]]
287 define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
288 ; CHECK-LABEL: test_cmpxchg_fail_order1:
290 %pair = cmpxchg i32* %addr, i32 %desired, i32 %new acquire acquire
291 %oldval = extractvalue { i32, i1 } %pair, 0
293 ; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
294 ; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
295 ; CHECK: cmp [[OLDVAL]], r1
296 ; CHECK: bne [[END_BB:\.?LBB[0-9]+_[0-9]+]]
297 ; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
298 ; CHECK: cmp [[SUCCESS]], #0
299 ; CHECK: bne [[LOOP_BB]]
307 define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
308 ; CHECK-LABEL: load_load_add_acquire
309 %val1 = load atomic i32* %mem1 acquire, align 4
310 %val2 = load atomic i32* %mem2 acquire, align 4
311 %tmp = add i32 %val1, %val2
313 ; CHECK: ldr {{r[0-9]}}, [r0]
315 ; CHECK: ldr {{r[0-9]}}, [r1]
319 ; CHECK-M0: ___sync_val_compare_and_swap_4
320 ; CHECK-M0: ___sync_val_compare_and_swap_4
322 ; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r0]
323 ; CHECK-BAREMETAL-NOT: dmb
324 ; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r1]
325 ; CHECK-BAREMETAL-NOT: dmb
326 ; CHECK-BAREMETAL: add r0,
331 define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
332 ; CHECK-LABEL: store_store_release
333 store atomic i32 %val1, i32* %mem1 release, align 4
334 store atomic i32 %val2, i32* %mem2 release, align 4
337 ; CHECK: str r1, [r0]
339 ; CHECK: str r3, [r2]
341 ; CHECK-M0: ___sync_lock_test_and_set
342 ; CHECK-M0: ___sync_lock_test_and_set
344 ; CHECK-BAREMETAL-NOT: dmb
345 ; CHECK-BAREMTEAL: str r1, [r0]
346 ; CHECK-BAREMETAL-NOT: dmb
347 ; CHECK-BAREMTEAL: str r3, [r2]
352 define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) {
353 ; CHECK-LABEL: load_fence_store_monotonic
354 %val = load atomic i32* %mem1 monotonic, align 4
356 store atomic i32 %val, i32* %mem2 monotonic, align 4
358 ; CHECK: ldr [[R0:r[0-9]]], [r0]
360 ; CHECK: str [[R0]], [r1]
362 ; CHECK-M0: ldr [[R0:r[0-9]]], [r0]
364 ; CHECK-M0: str [[R0]], [r1]
366 ; CHECK-BAREMETAL: ldr [[R0:r[0-9]]], [r0]
367 ; CHECK-BAREMETAL-NOT: dmb
368 ; CHECK-BAREMETAL: str [[R0]], [r1]