1 ; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
2 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
3 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
4 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
5 ; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
7 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
9 define void @func(i32 %argc, i8** %argv) nounwind {
11 %argc.addr = alloca i32 ; <i32*> [#uses=1]
12 %argv.addr = alloca i8** ; <i8***> [#uses=1]
13 %val1 = alloca i32 ; <i32*> [#uses=2]
14 %val2 = alloca i32 ; <i32*> [#uses=15]
15 %andt = alloca i32 ; <i32*> [#uses=2]
16 %ort = alloca i32 ; <i32*> [#uses=2]
17 %xort = alloca i32 ; <i32*> [#uses=2]
18 %old = alloca i32 ; <i32*> [#uses=18]
19 %temp = alloca i32 ; <i32*> [#uses=2]
20 store i32 %argc, i32* %argc.addr
21 store i8** %argv, i8*** %argv.addr
22 store i32 0, i32* %val1
23 store i32 31, i32* %val2
24 store i32 3855, i32* %andt
25 store i32 3855, i32* %ort
26 store i32 3855, i32* %xort
27 store i32 4, i32* %temp
28 %tmp = load i32, i32* %temp
32 ; CHECK-T1: blx ___sync_fetch_and_add_4
33 ; CHECK-M0: bl ___sync_fetch_and_add_4
34 ; CHECK-BAREMETAL: add
35 ; CHECK-BAREMETAL-NOT: __sync
36 %0 = atomicrmw add i32* %val1, i32 %tmp monotonic
37 store i32 %0, i32* %old
41 ; CHECK-T1: blx ___sync_fetch_and_sub_4
42 ; CHECK-M0: bl ___sync_fetch_and_sub_4
43 ; CHECK-BAREMETAL: sub
44 ; CHECK-BAREMETAL-NOT: __sync
45 %1 = atomicrmw sub i32* %val2, i32 30 monotonic
46 store i32 %1, i32* %old
50 ; CHECK-T1: blx ___sync_fetch_and_add_4
51 ; CHECK-M0: bl ___sync_fetch_and_add_4
52 ; CHECK-BAREMETAL: add
53 ; CHECK-BAREMETAL-NOT: __sync
54 %2 = atomicrmw add i32* %val2, i32 1 monotonic
55 store i32 %2, i32* %old
59 ; CHECK-T1: blx ___sync_fetch_and_sub_4
60 ; CHECK-M0: bl ___sync_fetch_and_sub_4
61 ; CHECK-BAREMETAL: sub
62 ; CHECK-BAREMETAL-NOT: __sync
63 %3 = atomicrmw sub i32* %val2, i32 1 monotonic
64 store i32 %3, i32* %old
68 ; CHECK-T1: blx ___sync_fetch_and_and_4
69 ; CHECK-M0: bl ___sync_fetch_and_and_4
70 ; CHECK-BAREMETAL: and
71 ; CHECK-BAREMETAL-NOT: __sync
72 %4 = atomicrmw and i32* %andt, i32 4080 monotonic
73 store i32 %4, i32* %old
77 ; CHECK-T1: blx ___sync_fetch_and_or_4
78 ; CHECK-M0: bl ___sync_fetch_and_or_4
80 ; CHECK-BAREMETAL-NOT: __sync
81 %5 = atomicrmw or i32* %ort, i32 4080 monotonic
82 store i32 %5, i32* %old
86 ; CHECK-T1: blx ___sync_fetch_and_xor_4
87 ; CHECK-M0: bl ___sync_fetch_and_xor_4
88 ; CHECK-BAREMETAL: eor
89 ; CHECK-BAREMETAL-NOT: __sync
90 %6 = atomicrmw xor i32* %xort, i32 4080 monotonic
91 store i32 %6, i32* %old
95 ; CHECK-T1: blx ___sync_fetch_and_min_4
96 ; CHECK-M0: bl ___sync_fetch_and_min_4
97 ; CHECK-BAREMETAL: cmp
98 ; CHECK-BAREMETAL-NOT: __sync
99 %7 = atomicrmw min i32* %val2, i32 16 monotonic
100 store i32 %7, i32* %old
105 ; CHECK-T1: blx ___sync_fetch_and_min_4
106 ; CHECK-M0: bl ___sync_fetch_and_min_4
107 ; CHECK-BAREMETAL: cmp
108 ; CHECK-BAREMETAL-NOT: __sync
109 %8 = atomicrmw min i32* %val2, i32 %neg monotonic
110 store i32 %8, i32* %old
114 ; CHECK-T1: blx ___sync_fetch_and_max_4
115 ; CHECK-M0: bl ___sync_fetch_and_max_4
116 ; CHECK-BAREMETAL: cmp
117 ; CHECK-BAREMETAL-NOT: __sync
118 %9 = atomicrmw max i32* %val2, i32 1 monotonic
119 store i32 %9, i32* %old
123 ; CHECK-T1: blx ___sync_fetch_and_max_4
124 ; CHECK-M0: bl ___sync_fetch_and_max_4
125 ; CHECK-BAREMETAL: cmp
126 ; CHECK-BAREMETAL-NOT: __sync
127 %10 = atomicrmw max i32* %val2, i32 0 monotonic
128 store i32 %10, i32* %old
132 ; CHECK-T1: blx ___sync_fetch_and_umin_4
133 ; CHECK-M0: bl ___sync_fetch_and_umin_4
134 ; CHECK-BAREMETAL: cmp
135 ; CHECK-BAREMETAL-NOT: __sync
136 %11 = atomicrmw umin i32* %val2, i32 16 monotonic
137 store i32 %11, i32* %old
142 ; CHECK-T1: blx ___sync_fetch_and_umin_4
143 ; CHECK-M0: bl ___sync_fetch_and_umin_4
144 ; CHECK-BAREMETAL: cmp
145 ; CHECK-BAREMETAL-NOT: __sync
146 %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
147 store i32 %12, i32* %old
151 ; CHECK-T1: blx ___sync_fetch_and_umax_4
152 ; CHECK-M0: bl ___sync_fetch_and_umax_4
153 ; CHECK-BAREMETAL: cmp
154 ; CHECK-BAREMETAL-NOT: __sync
155 %13 = atomicrmw umax i32* %val2, i32 1 monotonic
156 store i32 %13, i32* %old
160 ; CHECK-T1: blx ___sync_fetch_and_umax_4
161 ; CHECK-M0: bl ___sync_fetch_and_umax_4
162 ; CHECK-BAREMETAL: cmp
163 ; CHECK-BAREMETAL-NOT: __sync
164 %14 = atomicrmw umax i32* %val2, i32 0 monotonic
165 store i32 %14, i32* %old
170 define void @func2() nounwind {
174 store i16 31, i16* %val
178 ; CHECK-T1: blx ___sync_fetch_and_umin_2
179 ; CHECK-M0: bl ___sync_fetch_and_umin_2
180 ; CHECK-BAREMETAL: cmp
181 ; CHECK-BAREMETAL-NOT: __sync
182 %0 = atomicrmw umin i16* %val, i16 16 monotonic
183 store i16 %0, i16* %old
188 ; CHECK-T1: blx ___sync_fetch_and_umin_2
189 ; CHECK-M0: bl ___sync_fetch_and_umin_2
190 ; CHECK-BAREMETAL: cmp
191 ; CHECK-BAREMETAL-NOT: __sync
192 %1 = atomicrmw umin i16* %val, i16 %uneg monotonic
193 store i16 %1, i16* %old
197 ; CHECK-T1: blx ___sync_fetch_and_umax_2
198 ; CHECK-M0: bl ___sync_fetch_and_umax_2
199 ; CHECK-BAREMETAL: cmp
200 ; CHECK-BAREMETAL-NOT: __sync
201 %2 = atomicrmw umax i16* %val, i16 1 monotonic
202 store i16 %2, i16* %old
206 ; CHECK-T1: blx ___sync_fetch_and_umax_2
207 ; CHECK-M0: bl ___sync_fetch_and_umax_2
208 ; CHECK-BAREMETAL: cmp
209 ; CHECK-BAREMETAL-NOT: __sync
210 %3 = atomicrmw umax i16* %val, i16 0 monotonic
211 store i16 %3, i16* %old
215 define void @func3() nounwind {
219 store i8 31, i8* %val
223 ; CHECK-T1: blx ___sync_fetch_and_umin_1
224 ; CHECK-M0: bl ___sync_fetch_and_umin_1
225 ; CHECK-BAREMETAL: cmp
226 ; CHECK-BAREMETAL-NOT: __sync
227 %0 = atomicrmw umin i8* %val, i8 16 monotonic
228 store i8 %0, i8* %old
232 ; CHECK-T1: blx ___sync_fetch_and_umin_1
233 ; CHECK-M0: bl ___sync_fetch_and_umin_1
234 ; CHECK-BAREMETAL: cmp
235 ; CHECK-BAREMETAL-NOT: __sync
237 %1 = atomicrmw umin i8* %val, i8 %uneg monotonic
238 store i8 %1, i8* %old
242 ; CHECK-T1: blx ___sync_fetch_and_umax_1
243 ; CHECK-M0: bl ___sync_fetch_and_umax_1
244 ; CHECK-BAREMETAL: cmp
245 ; CHECK-BAREMETAL-NOT: __sync
246 %2 = atomicrmw umax i8* %val, i8 1 monotonic
247 store i8 %2, i8* %old
251 ; CHECK-T1: blx ___sync_fetch_and_umax_1
252 ; CHECK-M0: bl ___sync_fetch_and_umax_1
253 ; CHECK-BAREMETAL: cmp
254 ; CHECK-BAREMETAL-NOT: __sync
255 %3 = atomicrmw umax i8* %val, i8 0 monotonic
256 store i8 %3, i8* %old
261 ; This function should not need to use callee-saved registers.
262 ; rdar://problem/12203728
264 define i32 @func4(i32* %p) nounwind optsize ssp {
266 %0 = atomicrmw add i32* %p, i32 1 monotonic
270 define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
271 ; CHECK-LABEL: test_cmpxchg_fail_order:
273 %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
274 %oldval = extractvalue { i32, i1 } %pair, 0
276 ; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
277 ; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
278 ; CHECK: cmp [[OLDVAL]], r1
280 ; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
281 ; CHECK: cmp [[SUCCESS]], #0
282 ; CHECK: bne [[LOOP_BB]]
289 define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
290 ; CHECK-LABEL: test_cmpxchg_fail_order1:
292 %pair = cmpxchg i32* %addr, i32 %desired, i32 %new acquire acquire
293 %oldval = extractvalue { i32, i1 } %pair, 0
295 ; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
296 ; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
297 ; CHECK: cmp [[OLDVAL]], r1
298 ; CHECK: bne [[END_BB:\.?LBB[0-9]+_[0-9]+]]
299 ; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
300 ; CHECK: cmp [[SUCCESS]], #0
301 ; CHECK: bne [[LOOP_BB]]
309 define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
310 ; CHECK-LABEL: load_load_add_acquire
311 %val1 = load atomic i32, i32* %mem1 acquire, align 4
312 %val2 = load atomic i32, i32* %mem2 acquire, align 4
313 %tmp = add i32 %val1, %val2
315 ; CHECK: ldr {{r[0-9]}}, [r0]
317 ; CHECK: ldr {{r[0-9]}}, [r1]
321 ; CHECK-M0: ___sync_val_compare_and_swap_4
322 ; CHECK-M0: ___sync_val_compare_and_swap_4
324 ; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r0]
325 ; CHECK-BAREMETAL-NOT: dmb
326 ; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r1]
327 ; CHECK-BAREMETAL-NOT: dmb
328 ; CHECK-BAREMETAL: add r0,
333 define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
334 ; CHECK-LABEL: store_store_release
335 store atomic i32 %val1, i32* %mem1 release, align 4
336 store atomic i32 %val2, i32* %mem2 release, align 4
339 ; CHECK: str r1, [r0]
341 ; CHECK: str r3, [r2]
343 ; CHECK-M0: ___sync_lock_test_and_set
344 ; CHECK-M0: ___sync_lock_test_and_set
346 ; CHECK-BAREMETAL-NOT: dmb
347 ; CHECK-BAREMTEAL: str r1, [r0]
348 ; CHECK-BAREMETAL-NOT: dmb
349 ; CHECK-BAREMTEAL: str r3, [r2]
354 define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) {
355 ; CHECK-LABEL: load_fence_store_monotonic
356 %val = load atomic i32, i32* %mem1 monotonic, align 4
358 store atomic i32 %val, i32* %mem2 monotonic, align 4
360 ; CHECK: ldr [[R0:r[0-9]]], [r0]
362 ; CHECK: str [[R0]], [r1]
364 ; CHECK-M0: ldr [[R0:r[0-9]]], [r0]
366 ; CHECK-M0: str [[R0]], [r1]
368 ; CHECK-BAREMETAL: ldr [[R0:r[0-9]]], [r0]
369 ; CHECK-BAREMETAL-NOT: dmb
370 ; CHECK-BAREMETAL: str [[R0]], [r1]