1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
2 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s
3 ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
4 ; dependency) when it isn't dependent on last CPSR defining instruction.
7 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
10 ; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
11 ; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
12 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
13 %0 = mul nsw i32 %a, %b
14 %1 = mul nsw i32 %c, %d
15 %2 = mul nsw i32 %0, %1
19 ; Avoid partial CPSR dependency via loop backedge.
21 define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
24 %tobool7 = icmp eq i32* %ptr2, null
25 br i1 %tobool7, label %while.end, label %while.body
29 ; CHECK: mul r{{[0-9]+}}
31 %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
32 %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
33 %0 = load i32* %ptr1.addr.09, align 4
34 %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1
35 %1 = load i32* %arrayidx1, align 4
36 %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2
37 %2 = load i32* %arrayidx3, align 4
38 %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3
39 %3 = load i32* %arrayidx4, align 4
40 %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4
42 %mul5 = mul i32 %mul, %2
43 %mul6 = mul i32 %mul5, %3
44 store i32 %mul6, i32* %ptr2.addr.08, align 4
45 %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1
46 %tobool = icmp eq i32* %incdec.ptr, null
47 br i1 %tobool, label %while.end, label %while.body