1 ; RUN: llc -mtriple=thumbv7-netbsd-eabi -o - %s | FileCheck %s
4 ; ARM's frame lowering attempts to tack another callee-saved register onto the
5 ; list when it detects a potential misaligned VFP store. However, if there are
6 ; none available it used to just vpush anyway and misreport the location of the
7 ; registers in unwind info. Since there are benefits to aligned stores, it's
8 ; better to correct the code than the .cfi_offset directive.
10 define void @test_dpr_align(i8 %l, i8 %r) {
11 ; CHECK-LABEL: test_dpr_align:
12 ; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
15 ; CHECK: .cfi_offset d8, -48
22 ; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
23 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
28 ; The prologue (but not the epilogue) can be made more space efficient by
29 ; chucking an argument register into the list. Not worth it in general though,
30 ; "sub sp, #4" is likely faster.
31 define void @test_dpr_align_tiny(i8 %l, i8 %r) minsize {
32 ; CHECK-LABEL: test_dpr_align_tiny:
33 ; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr}
36 ; CHECK: .cfi_offset d8, -48
43 ; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
44 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
50 ; However, we shouldn't do a 2-step align/adjust if there are no DPRs to be
52 define void @test_nodpr_noalign(i8 %l, i8 %r) {
53 ; CHECK-LABEL: test_nodpr_noalign:
54 ; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
63 ; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
65 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()