1 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
2 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
3 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
4 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
5 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
6 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
7 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
9 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
10 ; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
13 ; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
14 ; and therefore must set flags. {{s?}} below denotes this, instead of
19 define i8 @zext_1_8(i1 %a) nounwind ssp {
22 ; prev6-LABEL: zext_1_8:
23 ; prev6: and r0, r0, #1
28 define i16 @zext_1_16(i1 %a) nounwind ssp {
29 ; v7-LABEL: zext_1_16:
31 ; prev6-LABEL: zext_1_16:
32 ; prev6: and r0, r0, #1
33 %r = zext i1 %a to i16
37 define i32 @zext_1_32(i1 %a) nounwind ssp {
38 ; v7-LABEL: zext_1_32:
40 ; prev6-LABEL: zext_1_32:
41 ; prev6: and r0, r0, #1
42 %r = zext i1 %a to i32
46 define i16 @zext_8_16(i8 %a) nounwind ssp {
47 ; v7-LABEL: zext_8_16:
48 ; v7: and r0, r0, #255
49 ; prev6-LABEL: zext_8_16:
50 ; prev6: and r0, r0, #255
51 %r = zext i8 %a to i16
55 define i32 @zext_8_32(i8 %a) nounwind ssp {
56 ; v7-LABEL: zext_8_32:
57 ; v7: and r0, r0, #255
58 ; prev6-LABEL: zext_8_32:
59 ; prev6: and r0, r0, #255
60 %r = zext i8 %a to i32
64 define i32 @zext_16_32(i16 %a) nounwind ssp {
65 ; v7-LABEL: zext_16_32:
67 ; prev6-LABEL: zext_16_32:
68 ; prev6: lsl{{s?}} r0, r0, #16
69 ; prev6: lsr{{s?}} r0, r0, #16
70 %r = zext i16 %a to i32
76 define i8 @sext_1_8(i1 %a) nounwind ssp {
78 ; v7: lsl{{s?}} r0, r0, #31
79 ; v7: asr{{s?}} r0, r0, #31
80 ; prev6-LABEL: sext_1_8:
81 ; prev6: lsl{{s?}} r0, r0, #31
82 ; prev6: asr{{s?}} r0, r0, #31
87 define i16 @sext_1_16(i1 %a) nounwind ssp {
88 ; v7-LABEL: sext_1_16:
89 ; v7: lsl{{s?}} r0, r0, #31
90 ; v7: asr{{s?}} r0, r0, #31
91 ; prev6-LABEL: sext_1_16:
92 ; prev6: lsl{{s?}} r0, r0, #31
93 ; prev6: asr{{s?}} r0, r0, #31
94 %r = sext i1 %a to i16
98 define i32 @sext_1_32(i1 %a) nounwind ssp {
99 ; v7-LABEL: sext_1_32:
100 ; v7: lsl{{s?}} r0, r0, #31
101 ; v7: asr{{s?}} r0, r0, #31
102 ; prev6-LABEL: sext_1_32:
103 ; prev6: lsl{{s?}} r0, r0, #31
104 ; prev6: asr{{s?}} r0, r0, #31
105 %r = sext i1 %a to i32
109 define i16 @sext_8_16(i8 %a) nounwind ssp {
110 ; v7-LABEL: sext_8_16:
112 ; prev6-LABEL: sext_8_16:
113 ; prev6: lsl{{s?}} r0, r0, #24
114 ; prev6: asr{{s?}} r0, r0, #24
115 %r = sext i8 %a to i16
119 define i32 @sext_8_32(i8 %a) nounwind ssp {
120 ; v7-LABEL: sext_8_32:
122 ; prev6-LABEL: sext_8_32:
123 ; prev6: lsl{{s?}} r0, r0, #24
124 ; prev6: asr{{s?}} r0, r0, #24
125 %r = sext i8 %a to i32
129 define i32 @sext_16_32(i16 %a) nounwind ssp {
130 ; v7-LABEL: sext_16_32:
132 ; prev6-LABEL: sext_16_32:
133 ; prev6: lsl{{s?}} r0, r0, #16
134 ; prev6: asr{{s?}} r0, r0, #16
135 %r = sext i16 %a to i32