1 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
2 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
3 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
4 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
5 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
6 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG
10 ; Note that some of these tests assume that relocations are either
11 ; movw/movt or constant pool loads. Different platforms will select
12 ; different approaches.
14 @message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
15 @temp = common global [60 x i8] zeroinitializer, align 1
17 define void @t1() nounwind ssp {
19 ; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}}
20 ; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
24 ; ARM: and r1, r1, #255
25 ; ARM: bl {{_?}}memset
27 ; ARM-LONG: {{(movw r3, :lower16:L_memset\$non_lazy_ptr)|(ldr r3, .LCPI)}}
28 ; ARM-LONG: {{(movt r3, :upper16:L_memset\$non_lazy_ptr)?}}
29 ; ARM-LONG: ldr r3, [r3]
32 ; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}}
33 ; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
39 ; THUMB: and r1, r1, #255
40 ; THUMB: bl {{_?}}memset
41 ; THUMB-LONG-LABEL: t1:
42 ; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
43 ; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
44 ; THUMB-LONG: ldr r3, [r3]
46 call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i32 4, i1 false)
50 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
52 define void @t2() nounwind ssp {
54 ; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
55 ; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
58 ; ARM: add r0, r0, #16
60 ; ARM: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
62 ; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
63 ; ARM: bl {{_?}}memcpy
65 ; ARM-LONG: {{(movw r3, :lower16:L_memcpy\$non_lazy_ptr)|(ldr r3, .LCPI)}}
66 ; ARM-LONG: {{(movt r3, :upper16:L_memcpy\$non_lazy_ptr)?}}
67 ; ARM-LONG: ldr r3, [r3]
70 ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
71 ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
73 ; THUMB: adds r1, r0, #4
77 ; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
79 ; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
80 ; THUMB: bl {{_?}}memcpy
81 ; THUMB-LONG-LABEL: t2:
82 ; THUMB-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr
83 ; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
84 ; THUMB-LONG: ldr r3, [r3]
86 call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 17, i32 4, i1 false)
90 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
92 define void @t3() nounwind ssp {
94 ; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
95 ; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
98 ; ARM: add r0, r0, #16
101 ; ARM: bl {{_?}}memmove
102 ; ARM-LONG-LABEL: t3:
103 ; ARM-LONG: {{(movw r3, :lower16:L_memmove\$non_lazy_ptr)|(ldr r3, .LCPI)}}
104 ; ARM-LONG: {{(movt r3, :upper16:L_memmove\$non_lazy_ptr)?}}
105 ; ARM-LONG: ldr r3, [r3]
108 ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
109 ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
110 ; THUMB: ldr r0, [r0]
111 ; THUMB: adds r1, r0, #4
112 ; THUMB: adds r0, #16
113 ; THUMB: movs r2, #10
115 ; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
117 ; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
118 ; THUMB: bl {{_?}}memmove
119 ; THUMB-LONG-LABEL: t3:
120 ; THUMB-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr
121 ; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
122 ; THUMB-LONG: ldr r3, [r3]
124 call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
128 define void @t4() nounwind ssp {
130 ; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
131 ; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
133 ; ARM: ldr r1, [r0, #16]
134 ; ARM: str r1, [r0, #4]
135 ; ARM: ldr r1, [r0, #20]
136 ; ARM: str r1, [r0, #8]
137 ; ARM: ldrh r1, [r0, #24]
138 ; ARM: strh r1, [r0, #12]
141 ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
142 ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
143 ; THUMB: ldr r0, [r0]
144 ; THUMB: ldr r1, [r0, #16]
145 ; THUMB: str r1, [r0, #4]
146 ; THUMB: ldr r1, [r0, #20]
147 ; THUMB: str r1, [r0, #8]
148 ; THUMB: ldrh r1, [r0, #24]
149 ; THUMB: strh r1, [r0, #12]
151 call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 4, i1 false)
155 declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
157 define void @t5() nounwind ssp {
159 ; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
160 ; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
162 ; ARM: ldrh r1, [r0, #16]
163 ; ARM: strh r1, [r0, #4]
164 ; ARM: ldrh r1, [r0, #18]
165 ; ARM: strh r1, [r0, #6]
166 ; ARM: ldrh r1, [r0, #20]
167 ; ARM: strh r1, [r0, #8]
168 ; ARM: ldrh r1, [r0, #22]
169 ; ARM: strh r1, [r0, #10]
170 ; ARM: ldrh r1, [r0, #24]
171 ; ARM: strh r1, [r0, #12]
174 ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
175 ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
176 ; THUMB: ldr r0, [r0]
177 ; THUMB: ldrh r1, [r0, #16]
178 ; THUMB: strh r1, [r0, #4]
179 ; THUMB: ldrh r1, [r0, #18]
180 ; THUMB: strh r1, [r0, #6]
181 ; THUMB: ldrh r1, [r0, #20]
182 ; THUMB: strh r1, [r0, #8]
183 ; THUMB: ldrh r1, [r0, #22]
184 ; THUMB: strh r1, [r0, #10]
185 ; THUMB: ldrh r1, [r0, #24]
186 ; THUMB: strh r1, [r0, #12]
188 call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 2, i1 false)
192 define void @t6() nounwind ssp {
194 ; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
195 ; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
197 ; ARM: ldrb r1, [r0, #16]
198 ; ARM: strb r1, [r0, #4]
199 ; ARM: ldrb r1, [r0, #17]
200 ; ARM: strb r1, [r0, #5]
201 ; ARM: ldrb r1, [r0, #18]
202 ; ARM: strb r1, [r0, #6]
203 ; ARM: ldrb r1, [r0, #19]
204 ; ARM: strb r1, [r0, #7]
205 ; ARM: ldrb r1, [r0, #20]
206 ; ARM: strb r1, [r0, #8]
207 ; ARM: ldrb r1, [r0, #21]
208 ; ARM: strb r1, [r0, #9]
209 ; ARM: ldrb r1, [r0, #22]
210 ; ARM: strb r1, [r0, #10]
211 ; ARM: ldrb r1, [r0, #23]
212 ; ARM: strb r1, [r0, #11]
213 ; ARM: ldrb r1, [r0, #24]
214 ; ARM: strb r1, [r0, #12]
215 ; ARM: ldrb r1, [r0, #25]
216 ; ARM: strb r1, [r0, #13]
219 ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
220 ; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
221 ; THUMB: ldr r0, [r0]
222 ; THUMB: ldrb r1, [r0, #16]
223 ; THUMB: strb r1, [r0, #4]
224 ; THUMB: ldrb r1, [r0, #17]
225 ; THUMB: strb r1, [r0, #5]
226 ; THUMB: ldrb r1, [r0, #18]
227 ; THUMB: strb r1, [r0, #6]
228 ; THUMB: ldrb r1, [r0, #19]
229 ; THUMB: strb r1, [r0, #7]
230 ; THUMB: ldrb r1, [r0, #20]
231 ; THUMB: strb r1, [r0, #8]
232 ; THUMB: ldrb r1, [r0, #21]
233 ; THUMB: strb r1, [r0, #9]
234 ; THUMB: ldrb r1, [r0, #22]
235 ; THUMB: strb r1, [r0, #10]
236 ; THUMB: ldrb r1, [r0, #23]
237 ; THUMB: strb r1, [r0, #11]
238 ; THUMB: ldrb r1, [r0, #24]
239 ; THUMB: strb r1, [r0, #12]
240 ; THUMB: ldrb r1, [r0, #25]
241 ; THUMB: strb r1, [r0, #13]
243 call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
248 define void @t7() nounwind ssp {
249 ; Just make sure this doesn't assert when we have an odd length and an alignment of 2.
250 call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 3, i32 2, i1 false)
254 define i32 @t8(i32 %x) nounwind {
257 ; ARM-NOT: FastISel missed call: %expval = call i32 @llvm.expect.i32(i32 %x, i32 1)
259 ; THUMB-NOT: FastISel missed call: %expval = call i32 @llvm.expect.i32(i32 %x, i32 1)
260 %expval = call i32 @llvm.expect.i32(i32 %x, i32 1)
264 declare i32 @llvm.expect.i32(i32, i32) nounwind readnone