1 ; RUN: llc -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK
3 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4 target triple = "armv7a--none-eabi"
6 ; CHECK-LABEL: test_vec3:
10 ; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}}
11 ; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]]
12 ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]]
13 ; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16
14 ; CHECK-DAG: strh [[RREG1]], [r0, #4]
15 ; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]
16 ; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]
18 define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
19 %H = sitofp i32 %i to half
20 %S = fadd half %H, 0xH4A00
21 %1 = insertelement <3 x half> undef, half %S, i32 0
22 %2 = insertelement <3 x half> %1, half %S, i32 1
23 %3 = insertelement <3 x half> %2, half %S, i32 2
24 store <3 x half> %3, <3 x half>* %arr, align 8
28 attributes #0 = { nounwind }