1 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s
5 ; Disable this optimization unless we know one of them is zero.
6 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
9 ; CHECK: vldr [[S0:s[0-9]+]],
10 ; CHECK: vldr [[S1:s[0-9]+]],
11 ; CHECK: vcmpe.f32 [[S1]], [[S0]]
12 ; CHECK: vmrs APSR_nzcv, fpscr
16 %2 = fcmp une float %0, %1
17 br i1 %2, label %bb1, label %bb2
28 ; If one side is zero, the other size sign bit is masked off to allow
30 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
34 ; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
35 ; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
37 ; CHECK: cmp [[REG1]], #0
38 ; CHECK: bfc [[REG2]], #31, #1
39 ; CHECK: cmpeq [[REG2]], #0
40 ; CHECK-NOT: vcmpe.f32
44 %1 = fcmp oeq double %0, 0.000000e+00
45 br i1 %1, label %bb1, label %bb2
56 define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
60 ; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
61 ; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
62 ; CHECK: tst [[REG3]], [[REG4]]
63 ; CHECK-NOT: vcmpe.f32
67 %1 = fcmp oeq float %0, 0.000000e+00
68 br i1 %1, label %bb1, label %bb2