1 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s
2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck -check-prefix=NAN %s
5 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
12 ; FINITE-NOT: vcmpe.f32
19 ; NAN: vcmpe.f32 s1, s0
20 ; NAN: vmrs apsr_nzcv, fpscr
24 %2 = fcmp une float %0, %1
25 br i1 %2, label %bb1, label %bb2
36 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
40 ; FINITE: ldrd r0, [r0]
43 ; FINITE: cmpeq r1, #0
44 ; FINITE-NOT: vcmpe.f32
48 %1 = fcmp oeq double %0, 0.000000e+00
49 br i1 %1, label %bb1, label %bb2
60 define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
64 ; FINITE: ldr r0, [r0]
66 ; FINITE-NOT: vcmpe.f32
70 %1 = fcmp oeq float %0, 0.000000e+00
71 br i1 %1, label %bb1, label %bb2