1 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=A8
2 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3
4 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC
5 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY
7 ; Magic ARM pair hints works best with linearscan / fast.
9 ; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base
10 ; register when interrupted or faulted.
12 @b = external global i64*
14 define i64 @t(i64 %a) nounwind readonly {
17 ; A8: ldrd r2, r3, [r2]
22 %0 = load i64** @b, align 4
23 %1 = load i64* %0, align 4
28 ; rdar://10435045 mixed LDRi8/LDRi12
30 ; In this case, LSR generate a sequence of LDRi8/LDRi12. We should be
31 ; able to generate an LDRD pair here, but this is highly sensitive to
32 ; regalloc hinting. So, this doubles as a register allocation
33 ; test. RABasic currently does a better job within the inner loop
34 ; because of its *lack* of hinting ability. Whereas RAGreedy keeps
35 ; R0/R1/R2 live as the three arguments, forcing the LDRD's odd
36 ; destination into R3. We then sensibly split LDRD again rather then
37 ; evict another live range or use callee saved regs. Sorry if the test
38 ; is sensitive to Regalloc changes, but it is an interesting case.
48 define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind {
50 %0 = add nsw i32 %n, -1 ; <i32> [#uses=2]
51 %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1]
52 br i1 %1, label %bb, label %return
54 bb: ; preds = %bb, %entry
55 %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3]
56 %scevgep = getelementptr i32* %a, i32 %i.03 ; <i32*> [#uses=1]
57 %scevgep4 = getelementptr i32* %b, i32 %i.03 ; <i32*> [#uses=1]
58 %tmp = add i32 %i.03, 1 ; <i32> [#uses=3]
59 %scevgep5 = getelementptr i32* %a, i32 %tmp ; <i32*> [#uses=1]
60 %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
61 %3 = load i32* %scevgep5, align 4 ; <i32> [#uses=1]
62 %4 = add nsw i32 %3, %2 ; <i32> [#uses=1]
63 store i32 %4, i32* %scevgep4, align 4
64 %exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1]
65 br i1 %exitcond, label %return, label %bb
67 return: ; preds = %bb, %entry