1 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=A8 -check-prefix=CHECK
2 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK
4 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK
5 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK
7 ; Magic ARM pair hints works best with linearscan / fast.
9 @b = external global i64*
11 ; We use the following two to force values into specific registers.
12 declare i64* @get_ptr()
13 declare void @use_i64(i64 %v)
15 define void @test_ldrd(i64 %a) nounwind readonly {
16 ; CHECK-LABEL: test_ldrd:
17 ; CHECK: bl{{x?}} _get_ptr
18 ; A8: ldrd r0, r1, [r0]
19 ; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base
20 ; register when interrupted or faulted.
21 ; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]]
22 ; CHECK: bl{{x?}} _use_i64
23 %ptr = call i64* @get_ptr()
24 %v = load i64, i64* %ptr, align 8
25 call void @use_i64(i64 %v)
29 ; rdar://10435045 mixed LDRi8/LDRi12
31 ; In this case, LSR generate a sequence of LDRi8/LDRi12. We should be
32 ; able to generate an LDRD pair here, but this is highly sensitive to
33 ; regalloc hinting. So, this doubles as a register allocation
34 ; test. RABasic currently does a better job within the inner loop
35 ; because of its *lack* of hinting ability. Whereas RAGreedy keeps
36 ; R0/R1/R2 live as the three arguments, forcing the LDRD's odd
37 ; destination into R3. We then sensibly split LDRD again rather then
38 ; evict another live range or use callee saved regs. Sorry if the test
39 ; is sensitive to Regalloc changes, but it is an interesting case.
49 define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind {
51 %0 = add nsw i32 %n, -1 ; <i32> [#uses=2]
52 %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1]
53 br i1 %1, label %bb, label %return
55 bb: ; preds = %bb, %entry
56 %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3]
57 %scevgep = getelementptr i32, i32* %a, i32 %i.03 ; <i32*> [#uses=1]
58 %scevgep4 = getelementptr i32, i32* %b, i32 %i.03 ; <i32*> [#uses=1]
59 %tmp = add i32 %i.03, 1 ; <i32> [#uses=3]
60 %scevgep5 = getelementptr i32, i32* %a, i32 %tmp ; <i32*> [#uses=1]
61 %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1]
62 %3 = load i32, i32* %scevgep5, align 4 ; <i32> [#uses=1]
63 %4 = add nsw i32 %3, %2 ; <i32> [#uses=1]
64 store i32 %4, i32* %scevgep4, align 4
65 %exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1]
66 br i1 %exitcond, label %return, label %bb
68 return: ; preds = %bb, %entry
73 ; Pair of loads not formed when lifetime markers are set.
74 %struct.Test = type { i32, i32, i32 }
76 @TestVar = external global %struct.Test
78 define void @Func1() nounwind ssp {
81 ; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
82 ; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}}
83 ; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4]
84 ; A8-NEXT: add [[FIELD1]], [[FIELD2]]
85 ; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}}
86 %orig_blocks = alloca [256 x i16], align 2
87 %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind
88 %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4
89 %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4
90 %add = add nsw i32 %tmp2, %tmp1
91 store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4
92 call void @llvm.lifetime.end(i64 512, i8* %0) nounwind
96 declare void @extfunc(i32, i32, i32, i32)
102 define void @Func2(i32* %p) {
104 %addr0 = getelementptr i32, i32* %p, i32 0
105 %addr1 = getelementptr i32, i32* %p, i32 1
106 %v0 = load i32, i32* %addr0
107 %v1 = load i32, i32* %addr1
108 ; try to force %v0/%v1 into non-adjacent registers
109 call void @extfunc(i32 %v0, i32 0, i32 0, i32 %v1)
113 declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
114 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind