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Add support for the ARM 't' register constraint. And another testcase
[oota-llvm.git]
/
test
/
CodeGen
/
ARM
/
ret_arg4.ll
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; RUN: llc < %s -march=arm
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define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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ret i32 %a4
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}