1 ; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM
2 ; RUN: llc < %s -march=arm -mcpu=arm1156t2-s -mattr=+thumb2 | \
3 ; RUN: FileCheck %s --check-prefix=ARMT2
4 ; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | \
5 ; RUN: FileCheck %s --check-prefix=THUMB2
7 define i32 @t1(i32 %c) nounwind readnone {
10 ; ARM: mov [[R1:r[0-9]+]], #101
11 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
12 ; ARM: movgt {{r[0-1]}}, #123
15 ; ARMT2: movw [[R:r[0-1]]], #357
16 ; ARMT2: movwgt [[R]], #123
19 ; THUMB2: movw [[R:r[0-1]]], #357
20 ; THUMB2: movgt [[R]], #123
22 %0 = icmp sgt i32 %c, 1
23 %1 = select i1 %0, i32 123, i32 357
27 define i32 @t2(i32 %c) nounwind readnone {
30 ; ARM: mov [[R:r[0-9]+]], #101
31 ; ARM: orr [[R]], [[R]], #256
32 ; ARM: movle [[R]], #123
35 ; ARMT2: mov [[R:r[0-1]]], #123
36 ; ARMT2: movwgt [[R]], #357
39 ; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123
40 ; THUMB2: movwgt [[R]], #357
42 %0 = icmp sgt i32 %c, 1
43 %1 = select i1 %0, i32 357, i32 123
47 define i32 @t3(i32 %a) nounwind readnone {
50 ; ARM: mov [[R:r[0-1]]], #0
51 ; ARM: moveq [[R]], #1
54 ; ARMT2: mov [[R:r[0-1]]], #0
55 ; ARMT2: movweq [[R]], #1
58 ; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #0
59 ; THUMB2: moveq [[R]], #1
60 %0 = icmp eq i32 %a, 160
61 %1 = zext i1 %0 to i32
65 define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
72 ; ARMT2: movwlt [[R0:r[0-9]+]], #65365
73 ; ARMT2: movtlt [[R0]], #65365
76 ; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
77 %0 = icmp slt i32 %a, %b
78 %1 = select i1 %0, i32 4283826005, i32 %x
83 define i32 @t5(i32 %a) nounwind {
95 ; THUMB2: movne r0, #0
96 %cmp = icmp eq i32 %a, 1
97 %conv = zext i1 %cmp to i32
101 define i32 @t6(i32 %a) nounwind {
112 ; THUMB2: movne r0, #1
113 %tobool = icmp ne i32 %a, 0
114 %lnot.ext = zext i1 %tobool to i32