1 ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
2 ; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
5 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
7 ; ARM: sub r0, r1, #-2147483647
11 ; T2: mvn r0, #-2147483648
14 %tmp1 = icmp sgt i32 %c, 10
15 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647
16 %tmp3 = add i32 %tmp2, %b
20 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
22 ; ARM: sub r0, r1, #10
26 ; T2: sub.w r0, r1, #10
28 %tmp1 = icmp sgt i32 %c, 10
29 %tmp2 = select i1 %tmp1, i32 0, i32 10
30 %tmp3 = sub i32 %b, %tmp2
34 define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
41 ; T2: and.w r0, r2, r3
42 %cond = icmp slt i32 %a, %b
43 %z = select i1 %cond, i32 -1, i32 %x
48 define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
55 ; T2: orr.w r0, r2, r3
56 %cond = icmp slt i32 %a, %b
57 %z = select i1 %cond, i32 0, i32 %x
62 define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
66 ; ARM: orreq r2, r2, #1
70 ; T2: orreq r2, r2, #1
71 %tmp1 = icmp eq i32 %a, %b
72 %tmp2 = zext i1 %tmp1 to i32
73 %tmp3 = or i32 %tmp2, %c
77 define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
80 ; ARM: eorlt r3, r3, r2
84 ; T2: eorlt.w r3, r3, r2
85 %cond = icmp slt i32 %a, %b
86 %tmp1 = select i1 %cond, i32 %c, i32 0
87 %tmp2 = xor i32 %tmp1, %d
91 define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
95 ; ARM: andeq r2, r2, r2, lsl #1
99 ; T2: andeq.w r2, r2, r2, lsl #1
100 %tmp1 = shl i32 %c, 1
101 %cond = icmp eq i32 %a, %b
102 %tmp2 = select i1 %cond, i32 %tmp1, i32 -1
103 %tmp3 = and i32 %c, %tmp2