1 ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
2 ; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
5 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
7 ; ARM: suble r1, r1, #-2147483647
11 ; T2: mvn r0, #-2147483648
14 %tmp1 = icmp sgt i32 %c, 10
15 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647
16 %tmp3 = add i32 %tmp2, %b
20 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
22 ; ARM: suble r1, r1, #10
28 %tmp1 = icmp sgt i32 %c, 10
29 %tmp2 = select i1 %tmp1, i32 0, i32 10
30 %tmp3 = sub i32 %b, %tmp2
34 define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
36 ; ARM: andge r3, r3, r2
42 %cond = icmp slt i32 %a, %b
43 %z = select i1 %cond, i32 -1, i32 %x
48 define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
50 ; ARM: orrge r3, r3, r2
56 %cond = icmp slt i32 %a, %b
57 %z = select i1 %cond, i32 0, i32 %x
62 define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
66 ; ARM: orreq r2, r2, #1
70 ; T2: orreq r2, r2, #1
71 %tmp1 = icmp eq i32 %a, %b
72 %tmp2 = zext i1 %tmp1 to i32
73 %tmp3 = or i32 %tmp2, %c
77 define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
80 ; ARM: eorlt r3, r3, r2
85 %cond = icmp slt i32 %a, %b
86 %tmp1 = select i1 %cond, i32 %c, i32 0
87 %tmp2 = xor i32 %tmp1, %d
91 define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
95 ; ARM: andeq r2, r2, r2, lsl #1
99 ; T2: andeq.w r2, r2, r2, lsl #1
100 %tmp1 = shl i32 %c, 1
101 %cond = icmp eq i32 %a, %b
102 %tmp2 = select i1 %cond, i32 %tmp1, i32 -1
103 %tmp3 = and i32 %c, %tmp2
107 ; Fold ORRri into movcc.
108 define i32 @t8(i32 %a, i32 %b) nounwind {
111 ; ARM: orrge r0, r1, #1
115 ; T2: orrge r0, r1, #1
117 %cond = icmp slt i32 %a, %b
118 %tmp1 = select i1 %cond, i32 %a, i32 %x
122 ; Fold ANDrr into movcc.
123 define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
126 ; ARM: andge r0, r1, r2
130 ; T2: andge.w r0, r1, r2
132 %cond = icmp slt i32 %a, %b
133 %tmp1 = select i1 %cond, i32 %a, i32 %x
137 ; Fold EORrs into movcc.
138 define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
141 ; ARM: eorge r0, r1, r2, lsl #7
145 ; T2: eorge.w r0, r1, r2, lsl #7
148 %cond = icmp slt i32 %a, %b
149 %tmp1 = select i1 %cond, i32 %a, i32 %x
153 ; Fold ORRri into movcc, reversing the condition.
154 define i32 @t11(i32 %a, i32 %b) nounwind {
157 ; ARM: orrlt r0, r1, #1
161 ; T2: orrlt r0, r1, #1
163 %cond = icmp slt i32 %a, %b
164 %tmp1 = select i1 %cond, i32 %x, i32 %a
168 ; Fold ADDri12 into movcc
169 define i32 @t12(i32 %a, i32 %b) nounwind {
176 ; T2: addwge r0, r1, #3000
177 %x = add i32 %b, 3000
178 %cond = icmp slt i32 %a, %b
179 %tmp1 = select i1 %cond, i32 %a, i32 %x
183 ; Handle frame index operands.
184 define void @pr13628() nounwind uwtable align 2 {
185 %x3 = alloca i8, i32 256, align 8
186 %x4 = load i8* undef, align 1
187 %x5 = icmp ne i8 %x4, 0
188 %x6 = select i1 %x5, i8* %x3, i8* null
189 call void @bar(i8* %x6) nounwind
192 declare void @bar(i8*)
194 ; Fold zext i1 into predicated add
195 define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
199 ; ARM: addgt r0, r0, #1
204 %cmp = icmp sgt i32 %a, 10
205 %conv = zext i1 %cmp to i32
206 %add = add i32 %conv, %c
210 ; Fold sext i1 into predicated sub
211 define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {
215 ; ARM: subgt r0, r0, #1
220 %cmp = icmp sgt i32 %a, 10
221 %conv = sext i1 %cmp to i32
222 %add = add i32 %conv, %c