1 ; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s
2 ; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC
4 ; Release operations only need the store barrier provided by a "dmb ishst",
6 define void @test_store_release(i32* %p, i32 %v) {
7 ; CHECK-LABEL: test_store_release:
11 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
12 store atomic i32 %v, i32* %p release, align 4
16 ; However, if sequential consistency is needed *something* must ensure a release
17 ; followed by an acquire does not get reordered. In that case a "dmb ishst" is
19 define i32 @test_seq_cst(i32* %p, i32 %v) {
20 ; CHECK-LABEL: test_seq_cst:
27 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
28 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
30 store atomic i32 %v, i32* %p seq_cst, align 4
31 %val = load atomic i32* %p seq_cst, align 4
35 ; Also, pure acquire operations should definitely not have an ishst barrier.
37 define i32 @test_acq(i32* %addr) {
38 ; CHECK-LABEL: test_acq:
42 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
43 %val = load atomic i32* %addr acquire, align 4