1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
5 ;Check the (default) alignment value.
6 ;CHECK: vld1.8 {d16[3]}, [r0]
7 %tmp1 = load <8 x i8>* %B
8 %tmp2 = load i8* %A, align 8
9 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3
13 define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
15 ;Check the alignment value. Max for this instruction is 16 bits:
16 ;CHECK: vld1.16 {d16[2]}, [r0, :16]
17 %tmp1 = load <4 x i16>* %B
18 %tmp2 = load i16* %A, align 8
19 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2
23 define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
25 ;Check the alignment value. Max for this instruction is 32 bits:
26 ;CHECK: vld1.32 {d16[1]}, [r0, :32]
27 %tmp1 = load <2 x i32>* %B
28 %tmp2 = load i32* %A, align 8
29 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
33 define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
35 ;CHECK: vld1.32 {d16[1]}, [r0]
36 %tmp1 = load <2 x float>* %B
37 %tmp2 = load float* %A, align 4
38 %tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1
42 define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
44 ;CHECK: vld1.8 {d17[1]}, [r0]
45 %tmp1 = load <16 x i8>* %B
46 %tmp2 = load i8* %A, align 8
47 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9
51 define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
53 ;CHECK: vld1.16 {d17[1]}, [r0, :16]
54 %tmp1 = load <8 x i16>* %B
55 %tmp2 = load i16* %A, align 8
56 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5
60 define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
62 ;CHECK: vld1.32 {d17[1]}, [r0, :32]
63 %tmp1 = load <4 x i32>* %B
64 %tmp2 = load i32* %A, align 8
65 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3
69 define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
71 ;CHECK: vld1.32 {d16[0]}, [r0]
72 %tmp1 = load <4 x float>* %B
73 %tmp2 = load float* %A
74 %tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0
78 %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
79 %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
80 %struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
81 %struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
83 %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
84 %struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
85 %struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
87 define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
89 ;Check the alignment value. Max for this instruction is 16 bits:
90 ;CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16]
91 %tmp1 = load <8 x i8>* %B
92 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
93 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
94 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
95 %tmp5 = add <8 x i8> %tmp3, %tmp4
99 define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
101 ;Check the alignment value. Max for this instruction is 32 bits:
102 ;CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32]
103 %tmp0 = bitcast i16* %A to i8*
104 %tmp1 = load <4 x i16>* %B
105 %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
106 %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0
107 %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1
108 %tmp5 = add <4 x i16> %tmp3, %tmp4
112 define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
115 %tmp0 = bitcast i32* %A to i8*
116 %tmp1 = load <2 x i32>* %B
117 %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
118 %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
119 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
120 %tmp5 = add <2 x i32> %tmp3, %tmp4
124 ;Check for a post-increment updating load.
125 define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
126 ;CHECK: vld2lanei32_update:
127 ;CHECK: vld2.32 {d16[1], d17[1]}, [r1]!
129 %tmp0 = bitcast i32* %A to i8*
130 %tmp1 = load <2 x i32>* %B
131 %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
132 %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
133 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
134 %tmp5 = add <2 x i32> %tmp3, %tmp4
135 %tmp6 = getelementptr i32* %A, i32 2
136 store i32* %tmp6, i32** %ptr
140 define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
143 %tmp0 = bitcast float* %A to i8*
144 %tmp1 = load <2 x float>* %B
145 %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
146 %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0
147 %tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1
148 %tmp5 = fadd <2 x float> %tmp3, %tmp4
149 ret <2 x float> %tmp5
152 define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
153 ;CHECK: vld2laneQi16:
154 ;Check the (default) alignment.
155 ;CHECK: vld2.16 {d17[1], d19[1]}, [r0]
156 %tmp0 = bitcast i16* %A to i8*
157 %tmp1 = load <8 x i16>* %B
158 %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
159 %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0
160 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1
161 %tmp5 = add <8 x i16> %tmp3, %tmp4
165 define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
166 ;CHECK: vld2laneQi32:
167 ;Check the alignment value. Max for this instruction is 64 bits:
168 ;CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]
169 %tmp0 = bitcast i32* %A to i8*
170 %tmp1 = load <4 x i32>* %B
171 %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
172 %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0
173 %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1
174 %tmp5 = add <4 x i32> %tmp3, %tmp4
178 define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
181 %tmp0 = bitcast float* %A to i8*
182 %tmp1 = load <4 x float>* %B
183 %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
184 %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0
185 %tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1
186 %tmp5 = fadd <4 x float> %tmp3, %tmp4
187 ret <4 x float> %tmp5
190 declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
191 declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
192 declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
193 declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind readonly
195 declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
196 declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
197 declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind readonly
199 %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
200 %struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
201 %struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
202 %struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
204 %struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
205 %struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
206 %struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
208 define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
211 %tmp1 = load <8 x i8>* %B
212 %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
213 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
214 %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
215 %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
216 %tmp6 = add <8 x i8> %tmp3, %tmp4
217 %tmp7 = add <8 x i8> %tmp5, %tmp6
221 define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
223 ;Check the (default) alignment value. VLD3 does not support alignment.
224 ;CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0]
225 %tmp0 = bitcast i16* %A to i8*
226 %tmp1 = load <4 x i16>* %B
227 %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
228 %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0
229 %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1
230 %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2
231 %tmp6 = add <4 x i16> %tmp3, %tmp4
232 %tmp7 = add <4 x i16> %tmp5, %tmp6
236 define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
239 %tmp0 = bitcast i32* %A to i8*
240 %tmp1 = load <2 x i32>* %B
241 %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
242 %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0
243 %tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1
244 %tmp5 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 2
245 %tmp6 = add <2 x i32> %tmp3, %tmp4
246 %tmp7 = add <2 x i32> %tmp5, %tmp6
250 define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
253 %tmp0 = bitcast float* %A to i8*
254 %tmp1 = load <2 x float>* %B
255 %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
256 %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0
257 %tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1
258 %tmp5 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 2
259 %tmp6 = fadd <2 x float> %tmp3, %tmp4
260 %tmp7 = fadd <2 x float> %tmp5, %tmp6
261 ret <2 x float> %tmp7
264 define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
265 ;CHECK: vld3laneQi16:
266 ;Check the (default) alignment value. VLD3 does not support alignment.
267 ;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0]
268 %tmp0 = bitcast i16* %A to i8*
269 %tmp1 = load <8 x i16>* %B
270 %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
271 %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
272 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
273 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
274 %tmp6 = add <8 x i16> %tmp3, %tmp4
275 %tmp7 = add <8 x i16> %tmp5, %tmp6
279 ;Check for a post-increment updating load with register increment.
280 define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
281 ;CHECK: vld3laneQi16_update:
282 ;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r2], r1
284 %tmp0 = bitcast i16* %A to i8*
285 %tmp1 = load <8 x i16>* %B
286 %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
287 %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
288 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
289 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
290 %tmp6 = add <8 x i16> %tmp3, %tmp4
291 %tmp7 = add <8 x i16> %tmp5, %tmp6
292 %tmp8 = getelementptr i16* %A, i32 %inc
293 store i16* %tmp8, i16** %ptr
297 define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
298 ;CHECK: vld3laneQi32:
300 %tmp0 = bitcast i32* %A to i8*
301 %tmp1 = load <4 x i32>* %B
302 %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1)
303 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0
304 %tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1
305 %tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2
306 %tmp6 = add <4 x i32> %tmp3, %tmp4
307 %tmp7 = add <4 x i32> %tmp5, %tmp6
311 define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
314 %tmp0 = bitcast float* %A to i8*
315 %tmp1 = load <4 x float>* %B
316 %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
317 %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0
318 %tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1
319 %tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2
320 %tmp6 = fadd <4 x float> %tmp3, %tmp4
321 %tmp7 = fadd <4 x float> %tmp5, %tmp6
322 ret <4 x float> %tmp7
325 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
326 declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
327 declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
328 declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
330 declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
331 declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
332 declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
334 %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
335 %struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
336 %struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
337 %struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
339 %struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
340 %struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
341 %struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
343 define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
345 ;Check the alignment value. Max for this instruction is 32 bits:
346 ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
347 %tmp1 = load <8 x i8>* %B
348 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
349 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
350 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
351 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
352 %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
353 %tmp7 = add <8 x i8> %tmp3, %tmp4
354 %tmp8 = add <8 x i8> %tmp5, %tmp6
355 %tmp9 = add <8 x i8> %tmp7, %tmp8
359 ;Check for a post-increment updating load.
360 define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
361 ;CHECK: vld4lanei8_update:
362 ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]!
364 %tmp1 = load <8 x i8>* %B
365 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
366 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
367 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
368 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
369 %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
370 %tmp7 = add <8 x i8> %tmp3, %tmp4
371 %tmp8 = add <8 x i8> %tmp5, %tmp6
372 %tmp9 = add <8 x i8> %tmp7, %tmp8
373 %tmp10 = getelementptr i8* %A, i32 4
374 store i8* %tmp10, i8** %ptr
378 define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
380 ;Check that a power-of-two alignment smaller than the total size of the memory
381 ;being loaded is ignored.
382 ;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
383 %tmp0 = bitcast i16* %A to i8*
384 %tmp1 = load <4 x i16>* %B
385 %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4)
386 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0
387 %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1
388 %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2
389 %tmp6 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 3
390 %tmp7 = add <4 x i16> %tmp3, %tmp4
391 %tmp8 = add <4 x i16> %tmp5, %tmp6
392 %tmp9 = add <4 x i16> %tmp7, %tmp8
396 define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
398 ;Check the alignment value. An 8-byte alignment is allowed here even though
399 ;it is smaller than the total size of the memory being loaded.
400 ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :64]
401 %tmp0 = bitcast i32* %A to i8*
402 %tmp1 = load <2 x i32>* %B
403 %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8)
404 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0
405 %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1
406 %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2
407 %tmp6 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 3
408 %tmp7 = add <2 x i32> %tmp3, %tmp4
409 %tmp8 = add <2 x i32> %tmp5, %tmp6
410 %tmp9 = add <2 x i32> %tmp7, %tmp8
414 define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
417 %tmp0 = bitcast float* %A to i8*
418 %tmp1 = load <2 x float>* %B
419 %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
420 %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0
421 %tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1
422 %tmp5 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 2
423 %tmp6 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 3
424 %tmp7 = fadd <2 x float> %tmp3, %tmp4
425 %tmp8 = fadd <2 x float> %tmp5, %tmp6
426 %tmp9 = fadd <2 x float> %tmp7, %tmp8
427 ret <2 x float> %tmp9
430 define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
431 ;CHECK: vld4laneQi16:
432 ;Check the alignment value. Max for this instruction is 64 bits:
433 ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64]
434 %tmp0 = bitcast i16* %A to i8*
435 %tmp1 = load <8 x i16>* %B
436 %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16)
437 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0
438 %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1
439 %tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2
440 %tmp6 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 3
441 %tmp7 = add <8 x i16> %tmp3, %tmp4
442 %tmp8 = add <8 x i16> %tmp5, %tmp6
443 %tmp9 = add <8 x i16> %tmp7, %tmp8
447 define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
448 ;CHECK: vld4laneQi32:
449 ;Check the (default) alignment.
450 ;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
451 %tmp0 = bitcast i32* %A to i8*
452 %tmp1 = load <4 x i32>* %B
453 %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
454 %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0
455 %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1
456 %tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2
457 %tmp6 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 3
458 %tmp7 = add <4 x i32> %tmp3, %tmp4
459 %tmp8 = add <4 x i32> %tmp5, %tmp6
460 %tmp9 = add <4 x i32> %tmp7, %tmp8
464 define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
467 %tmp0 = bitcast float* %A to i8*
468 %tmp1 = load <4 x float>* %B
469 %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
470 %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0
471 %tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1
472 %tmp5 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 2
473 %tmp6 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 3
474 %tmp7 = fadd <4 x float> %tmp3, %tmp4
475 %tmp8 = fadd <4 x float> %tmp5, %tmp6
476 %tmp9 = fadd <4 x float> %tmp7, %tmp8
477 ret <4 x float> %tmp9
480 declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
481 declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
482 declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
483 declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
485 declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
486 declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
487 declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
489 ; Radar 8776599: If one of the operands to a QQQQ REG_SEQUENCE is a register
490 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
491 ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
492 ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
493 define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
494 ;CHECK: test_qqqq_regsequence_subreg
496 %tmp63 = extractvalue [6 x i64] %b, 5
497 %tmp64 = zext i64 %tmp63 to i128
498 %tmp65 = shl i128 %tmp64, 64
499 %ins67 = or i128 %tmp65, 0
500 %tmp78 = bitcast i128 %ins67 to <8 x i16>
501 %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2)
502 call void @llvm.trap()
506 declare void @llvm.trap() nounwind