1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <8 x i8> @v_movi8() nounwind {
6 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
9 define <4 x i16> @v_movi16a() nounwind {
12 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
16 define <4 x i16> @v_movi16b() nounwind {
19 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
22 define <2 x i32> @v_movi32a() nounwind {
25 ret <2 x i32> < i32 32, i32 32 >
29 define <2 x i32> @v_movi32b() nounwind {
32 ret <2 x i32> < i32 8192, i32 8192 >
36 define <2 x i32> @v_movi32c() nounwind {
39 ret <2 x i32> < i32 2097152, i32 2097152 >
42 ; 0x20000000 = 536870912
43 define <2 x i32> @v_movi32d() nounwind {
46 ret <2 x i32> < i32 536870912, i32 536870912 >
50 define <2 x i32> @v_movi32e() nounwind {
53 ret <2 x i32> < i32 8447, i32 8447 >
57 define <2 x i32> @v_movi32f() nounwind {
60 ret <2 x i32> < i32 2162687, i32 2162687 >
63 ; 0xff0000ff0000ffff = 18374687574888349695
64 define <1 x i64> @v_movi64() nounwind {
67 ret <1 x i64> < i64 18374687574888349695 >
70 define <16 x i8> @v_movQi8() nounwind {
73 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
76 define <8 x i16> @v_movQi16a() nounwind {
79 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
83 define <8 x i16> @v_movQi16b() nounwind {
86 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
89 define <4 x i32> @v_movQi32a() nounwind {
92 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
96 define <4 x i32> @v_movQi32b() nounwind {
99 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
103 define <4 x i32> @v_movQi32c() nounwind {
106 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
109 ; 0x20000000 = 536870912
110 define <4 x i32> @v_movQi32d() nounwind {
113 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
117 define <4 x i32> @v_movQi32e() nounwind {
120 ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
124 define <4 x i32> @v_movQi32f() nounwind {
127 ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
130 ; 0xff0000ff0000ffff = 18374687574888349695
131 define <2 x i64> @v_movQi64() nounwind {
134 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
137 ; Check for correct assembler printing for immediate values.
138 %struct.int8x8_t = type { <8 x i8> }
139 define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
142 ;CHECK: vmov.i8 d0, #0x80
143 %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
144 store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
148 define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
151 ;CHECK: vmov.i8 d0, #0xB5
152 %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
153 store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
157 define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
160 %tmp1 = load <8 x i8>* %A
161 %tmp2 = call <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8> %tmp1)
165 define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
168 %tmp1 = load <4 x i16>* %A
169 %tmp2 = call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %tmp1)
173 define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
176 %tmp1 = load <2 x i32>* %A
177 %tmp2 = call <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32> %tmp1)
181 define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
184 %tmp1 = load <8 x i8>* %A
185 %tmp2 = call <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8> %tmp1)
189 define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
192 %tmp1 = load <4 x i16>* %A
193 %tmp2 = call <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16> %tmp1)
197 define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
200 %tmp1 = load <2 x i32>* %A
201 %tmp2 = call <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32> %tmp1)
205 declare <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8>) nounwind readnone
206 declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone
207 declare <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32>) nounwind readnone
209 declare <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8>) nounwind readnone
210 declare <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16>) nounwind readnone
211 declare <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32>) nounwind readnone
213 define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
216 %tmp1 = load <8 x i16>* %A
217 %tmp2 = call <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16> %tmp1)
221 define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
224 %tmp1 = load <4 x i32>* %A
225 %tmp2 = call <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32> %tmp1)
229 define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
232 %tmp1 = load <2 x i64>* %A
233 %tmp2 = call <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64> %tmp1)
237 declare <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16>) nounwind readnone
238 declare <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32>) nounwind readnone
239 declare <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64>) nounwind readnone
241 define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
244 %tmp1 = load <8 x i16>* %A
245 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
249 define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
252 %tmp1 = load <4 x i32>* %A
253 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
257 define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
260 %tmp1 = load <2 x i64>* %A
261 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
265 define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
268 %tmp1 = load <8 x i16>* %A
269 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
273 define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
276 %tmp1 = load <4 x i32>* %A
277 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
281 define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
284 %tmp1 = load <2 x i64>* %A
285 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
289 define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
292 %tmp1 = load <8 x i16>* %A
293 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
297 define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
300 %tmp1 = load <4 x i32>* %A
301 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
305 define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
308 %tmp1 = load <2 x i64>* %A
309 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
313 declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
314 declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
315 declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
317 declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
318 declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
319 declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
321 declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
322 declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
323 declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone