1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
6 %tmp1 = load <8 x i8>* %A
7 %tmp2 = sub <8 x i8> zeroinitializer, %tmp1
11 define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
14 %tmp1 = load <4 x i16>* %A
15 %tmp2 = sub <4 x i16> zeroinitializer, %tmp1
19 define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
22 %tmp1 = load <2 x i32>* %A
23 %tmp2 = sub <2 x i32> zeroinitializer, %tmp1
27 define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
30 %tmp1 = load <2 x float>* %A
31 %tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
35 define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
38 %tmp1 = load <16 x i8>* %A
39 %tmp2 = sub <16 x i8> zeroinitializer, %tmp1
43 define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
46 %tmp1 = load <8 x i16>* %A
47 %tmp2 = sub <8 x i16> zeroinitializer, %tmp1
51 define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
54 %tmp1 = load <4 x i32>* %A
55 %tmp2 = sub <4 x i32> zeroinitializer, %tmp1
59 define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
62 %tmp1 = load <4 x float>* %A
63 %tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1