1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
6 %tmp1 = load <2 x i32>* %A
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
11 define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
14 %tmp1 = load <4 x i32>* %A
15 %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
19 define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
22 %tmp1 = load <2 x float>* %A
23 %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
27 define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
30 %tmp1 = load <4 x float>* %A
31 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
35 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
36 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
38 declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
39 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone