1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
6 %tmp1 = load <8 x i8>* %A
7 %tmp2 = load <8 x i8>* %B
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
12 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
15 %tmp1 = load <4 x i16>* %A
16 %tmp2 = load <4 x i16>* %B
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
21 define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
24 %tmp1 = load <2 x i32>* %A
25 %tmp2 = load <2 x i32>* %B
26 %tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
30 define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
33 %tmp1 = load <1 x i64>* %A
34 %tmp2 = load <1 x i64>* %B
35 %tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
39 define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
42 %tmp1 = load <8 x i8>* %A
43 %tmp2 = load <8 x i8>* %B
44 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
48 define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
51 %tmp1 = load <4 x i16>* %A
52 %tmp2 = load <4 x i16>* %B
53 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
57 define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
60 %tmp1 = load <2 x i32>* %A
61 %tmp2 = load <2 x i32>* %B
62 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
66 define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
69 %tmp1 = load <1 x i64>* %A
70 %tmp2 = load <1 x i64>* %B
71 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
75 define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
78 %tmp1 = load <16 x i8>* %A
79 %tmp2 = load <16 x i8>* %B
80 %tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
84 define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
87 %tmp1 = load <8 x i16>* %A
88 %tmp2 = load <8 x i16>* %B
89 %tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
93 define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
96 %tmp1 = load <4 x i32>* %A
97 %tmp2 = load <4 x i32>* %B
98 %tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
102 define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
105 %tmp1 = load <2 x i64>* %A
106 %tmp2 = load <2 x i64>* %B
107 %tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
111 define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
114 %tmp1 = load <16 x i8>* %A
115 %tmp2 = load <16 x i8>* %B
116 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
120 define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
123 %tmp1 = load <8 x i16>* %A
124 %tmp2 = load <8 x i16>* %B
125 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
129 define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
132 %tmp1 = load <4 x i32>* %A
133 %tmp2 = load <4 x i32>* %B
134 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
138 define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
141 %tmp1 = load <2 x i64>* %A
142 %tmp2 = load <2 x i64>* %B
143 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
147 ; For left shifts by immediates, the signedness is irrelevant.
148 ; Test a mix of both signed and unsigned intrinsics.
150 define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
153 %tmp1 = load <8 x i8>* %A
154 %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
158 define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
161 %tmp1 = load <4 x i16>* %A
162 %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
166 define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
169 %tmp1 = load <2 x i32>* %A
170 %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
174 define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
177 %tmp1 = load <1 x i64>* %A
178 %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
182 define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
185 %tmp1 = load <16 x i8>* %A
186 %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
190 define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
193 %tmp1 = load <8 x i16>* %A
194 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
198 define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
201 %tmp1 = load <4 x i32>* %A
202 %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
206 define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
209 %tmp1 = load <2 x i64>* %A
210 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
214 ; Right shift by immediate:
216 define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
219 %tmp1 = load <8 x i8>* %A
220 %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
224 define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
227 %tmp1 = load <4 x i16>* %A
228 %tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
232 define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
235 %tmp1 = load <2 x i32>* %A
236 %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
240 define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
243 %tmp1 = load <1 x i64>* %A
244 %tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
248 define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
251 %tmp1 = load <8 x i8>* %A
252 %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
256 define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
259 %tmp1 = load <4 x i16>* %A
260 %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
264 define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
267 %tmp1 = load <2 x i32>* %A
268 %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
272 define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
275 %tmp1 = load <1 x i64>* %A
276 %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
280 define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
283 %tmp1 = load <16 x i8>* %A
284 %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
288 define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
291 %tmp1 = load <8 x i16>* %A
292 %tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
296 define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
299 %tmp1 = load <4 x i32>* %A
300 %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
304 define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
307 %tmp1 = load <2 x i64>* %A
308 %tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
312 define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
315 %tmp1 = load <16 x i8>* %A
316 %tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
320 define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
323 %tmp1 = load <8 x i16>* %A
324 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
328 define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
331 %tmp1 = load <4 x i32>* %A
332 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
336 define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
339 %tmp1 = load <2 x i64>* %A
340 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
344 declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
345 declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
346 declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
347 declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
349 declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
350 declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
351 declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
352 declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
354 declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
355 declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
356 declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
357 declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
359 declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
360 declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
361 declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
362 declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone