1 ; RUN: llc -mtriple=armv8 -mcpu=cyclone < %s | FileCheck %s --check-prefix=CHECK-CYCLONE
2 ; RUN: llc -mtriple=armv8 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-SWIFT
4 declare arm_aapcs_vfpcc void @take_vec64(<2 x i32>)
6 define void @test_vec64() {
7 ; CHECK-CYCLONE-LABEL: test_vec64:
8 ; CHECK-SWIFT-LABEL: test_vec64:
10 call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>)
11 call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>)
12 ; CHECK-CYCLONE-NOT: vmov.f64 d0,
13 ; CHECK-CYCLONE: vmov.i32 d0, #0
15 ; CHECK-CYCLONE: vmov.i32 d0, #0
18 ; CHECK-SWIFT: vmov.f64 [[ZEROREG:d[0-9]+]],
19 ; CHECK-SWIFT: vmov.i32 [[ZEROREG]], #0
20 ; CHECK-SWIFT: vorr d0, [[ZEROREG]], [[ZEROREG]]
22 ; CHECK-SWIFT: vorr d0, [[ZEROREG]], [[ZEROREG]]
28 declare arm_aapcs_vfpcc void @take_vec128(<8 x i16>)
30 define void @test_vec128() {
31 ; CHECK-CYCLONE-LABEL: test_vec128:
32 ; CHECK-SWIFT-LABEL: test_vec128:
34 call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
35 call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
36 ; CHECK-CYCLONE-NOT: vmov.f64 [[ZEROREG:d[0-9]+]],
37 ; CHECK-CYCLONE: vmov.i32 q0, #0
39 ; CHECK-CYCLONE: vmov.i32 q0, #0
42 ; CHECK-SWIFT-NOT: vmov.f64 [[ZEROREG:d[0-9]+]],
43 ; CHECK-SWIFT: vmov.i32 [[ZEROREG:q[0-9]+]], #0
44 ; CHECK-SWIFT: vorr q0, [[ZEROREG]], [[ZEROREG]]
46 ; CHECK-SWIFT: vorr q0, [[ZEROREG]], [[ZEROREG]]
52 declare void @take_i32(i32)
54 define void @test_i32() {
55 ; CHECK-CYCLONE-LABEL: test_i32:
56 ; CHECK-SWIFT-LABEL: test_i32:
58 call arm_aapcs_vfpcc void @take_i32(i32 0)
59 call arm_aapcs_vfpcc void @take_i32(i32 0)
60 ; CHECK-CYCLONE-NOT: vmov.f64 [[ZEROREG:d[0-9]+]],
61 ; CHECK-CYCLONE: mov r0, #0
63 ; CHECK-CYCLONE: mov r0, #0
66 ; It doesn't particularly matter what Swift does here, there isn't carefully
67 ; crafted behaviour that we might break in Cyclone.