1 ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s
3 define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
5 ; CHECK: add.2d v[[REG:[0-9]+]], v0, v1
6 ; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1
7 ; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1
8 %add = add <2 x i64> %a, %b
9 %vgetq_lane = extractelement <2 x i64> %add, i32 0
10 %vgetq_lane2 = extractelement <2 x i64> %b, i32 0
11 %add3 = add i64 %vgetq_lane, %vgetq_lane2
12 %sub = sub i64 %vgetq_lane, %vgetq_lane2
13 %vecinit = insertelement <2 x i64> undef, i64 %add3, i32 0
14 %vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 1
15 ret <2 x i64> %vecinit8
18 define double @subdd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
19 ; CHECK-LABEL: subdd_su64:
20 ; CHECK: sub d0, d1, d0
22 %vecext = extractelement <2 x i64> %a, i32 0
23 %vecext1 = extractelement <2 x i64> %b, i32 0
24 %sub.i = sub nsw i64 %vecext1, %vecext
25 %retval = bitcast i64 %sub.i to double
29 define double @vaddd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
30 ; CHECK-LABEL: vaddd_su64:
31 ; CHECK: add d0, d1, d0
33 %vecext = extractelement <2 x i64> %a, i32 0
34 %vecext1 = extractelement <2 x i64> %b, i32 0
35 %add.i = add nsw i64 %vecext1, %vecext
36 %retval = bitcast i64 %add.i to double