1 ; RUN: llc < %s -march=arm64 -verify-machineinstrs -mcpu=cyclone | FileCheck %s
3 define i32 @val_compare_and_swap(i32* %p) {
4 ; CHECK-LABEL: val_compare_and_swap:
5 ; CHECK: orr [[NEWVAL_REG:w[0-9]+]], wzr, #0x4
6 ; CHECK: orr [[OLDVAL_REG:w[0-9]+]], wzr, #0x7
7 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
8 ; CHECK: ldaxr [[RESULT:w[0-9]+]], [x0]
9 ; CHECK: cmp [[RESULT]], [[OLDVAL_REG]]
10 ; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
11 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[NEWVAL_REG]], [x0]
12 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
14 %val = cmpxchg i32* %p, i32 7, i32 4 acquire acquire
18 define i64 @val_compare_and_swap_64(i64* %p) {
19 ; CHECK-LABEL: val_compare_and_swap_64:
20 ; CHECK: orr [[NEWVAL_REG:x[0-9]+]], xzr, #0x4
21 ; CHECK: orr [[OLDVAL_REG:x[0-9]+]], xzr, #0x7
22 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
23 ; CHECK: ldxr [[RESULT:x[0-9]+]], [x0]
24 ; CHECK: cmp [[RESULT]], [[OLDVAL_REG]]
25 ; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
26 ; CHECK-NOT: stxr [[NEWVAL_REG]], [[NEWVAL_REG]]
27 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[NEWVAL_REG]], [x0]
28 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
30 %val = cmpxchg i64* %p, i64 7, i64 4 monotonic monotonic
34 define i32 @fetch_and_nand(i32* %p) {
35 ; CHECK-LABEL: fetch_and_nand:
36 ; CHECK: orr [[OLDVAL_REG:w[0-9]+]], wzr, #0x7
37 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
38 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
39 ; CHECK: bic [[SCRATCH2_REG:w[0-9]+]], [[OLDVAL_REG]], w[[DEST_REG]]
40 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
41 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
42 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
43 ; CHECK: mov x0, x[[DEST_REG]]
44 %val = atomicrmw nand i32* %p, i32 7 release
48 define i64 @fetch_and_nand_64(i64* %p) {
49 ; CHECK-LABEL: fetch_and_nand_64:
50 ; CHECK: orr [[OLDVAL_REG:x[0-9]+]], xzr, #0x7
51 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
52 ; CHECK: ldaxr [[DEST_REG:x[0-9]+]], [x0]
53 ; CHECK: bic [[SCRATCH2_REG:x[0-9]+]], [[OLDVAL_REG]], [[DEST_REG]]
54 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
55 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
56 ; CHECK: mov x0, [[DEST_REG]]
57 %val = atomicrmw nand i64* %p, i64 7 acq_rel
61 define i32 @fetch_and_or(i32* %p) {
62 ; CHECK-LABEL: fetch_and_or:
63 ; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #5
64 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
65 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
66 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
67 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
68 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
69 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
70 ; CHECK: mov x0, x[[DEST_REG]]
71 %val = atomicrmw or i32* %p, i32 5 seq_cst
75 define i64 @fetch_and_or_64(i64* %p) {
76 ; CHECK: fetch_and_or_64:
77 ; CHECK: orr [[OLDVAL_REG:x[0-9]+]], xzr, #0x7
78 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
79 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x0]
80 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], [[OLDVAL_REG]]
81 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
82 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
83 ; CHECK: mov x0, [[DEST_REG]]
84 %val = atomicrmw or i64* %p, i64 7 monotonic
88 define void @acquire_fence() {
91 ; CHECK-LABEL: acquire_fence:
95 define void @release_fence() {
98 ; CHECK-LABEL: release_fence:
102 define void @seq_cst_fence() {
105 ; CHECK-LABEL: seq_cst_fence:
106 ; CHECK: dmb ish{{$}}
109 define i32 @atomic_load(i32* %p) {
110 %r = load atomic i32* %p seq_cst, align 4
112 ; CHECK-LABEL: atomic_load:
116 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
117 ; CHECK-LABEL: atomic_load_relaxed_8:
118 %ptr_unsigned = getelementptr i8* %p, i32 4095
119 %val_unsigned = load atomic i8* %ptr_unsigned monotonic, align 1
120 ; CHECK: ldrb {{w[0-9]+}}, [x0, #4095]
122 %ptr_regoff = getelementptr i8* %p, i32 %off32
123 %val_regoff = load atomic i8* %ptr_regoff unordered, align 1
124 %tot1 = add i8 %val_unsigned, %val_regoff
125 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
126 ; CHECK: ldrb {{w[0-9]+}}, [x0, x1, sxtw]
128 %ptr_unscaled = getelementptr i8* %p, i32 -256
129 %val_unscaled = load atomic i8* %ptr_unscaled monotonic, align 1
130 %tot2 = add i8 %tot1, %val_unscaled
131 ; CHECK: ldurb {{w[0-9]+}}, [x0, #-256]
133 %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
134 %val_random = load atomic i8* %ptr_random unordered, align 1
135 %tot3 = add i8 %tot2, %val_random
136 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
137 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
142 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
143 ; CHECK-LABEL: atomic_load_relaxed_16:
144 %ptr_unsigned = getelementptr i16* %p, i32 4095
145 %val_unsigned = load atomic i16* %ptr_unsigned monotonic, align 2
146 ; CHECK: ldrh {{w[0-9]+}}, [x0, #8190]
148 %ptr_regoff = getelementptr i16* %p, i32 %off32
149 %val_regoff = load atomic i16* %ptr_regoff unordered, align 2
150 %tot1 = add i16 %val_unsigned, %val_regoff
151 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
152 ; CHECK: ldrh {{w[0-9]+}}, [x0, x1, sxtw #1]
154 %ptr_unscaled = getelementptr i16* %p, i32 -128
155 %val_unscaled = load atomic i16* %ptr_unscaled monotonic, align 2
156 %tot2 = add i16 %tot1, %val_unscaled
157 ; CHECK: ldurh {{w[0-9]+}}, [x0, #-256]
159 %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
160 %val_random = load atomic i16* %ptr_random unordered, align 2
161 %tot3 = add i16 %tot2, %val_random
162 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
163 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
168 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
169 ; CHECK-LABEL: atomic_load_relaxed_32:
170 %ptr_unsigned = getelementptr i32* %p, i32 4095
171 %val_unsigned = load atomic i32* %ptr_unsigned monotonic, align 4
172 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
174 %ptr_regoff = getelementptr i32* %p, i32 %off32
175 %val_regoff = load atomic i32* %ptr_regoff unordered, align 4
176 %tot1 = add i32 %val_unsigned, %val_regoff
177 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
178 ; CHECK: ldr {{w[0-9]+}}, [x0, x1, sxtw #2]
180 %ptr_unscaled = getelementptr i32* %p, i32 -64
181 %val_unscaled = load atomic i32* %ptr_unscaled monotonic, align 4
182 %tot2 = add i32 %tot1, %val_unscaled
183 ; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
185 %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
186 %val_random = load atomic i32* %ptr_random unordered, align 4
187 %tot3 = add i32 %tot2, %val_random
188 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
189 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
194 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
195 ; CHECK-LABEL: atomic_load_relaxed_64:
196 %ptr_unsigned = getelementptr i64* %p, i32 4095
197 %val_unsigned = load atomic i64* %ptr_unsigned monotonic, align 8
198 ; CHECK: ldr {{x[0-9]+}}, [x0, #32760]
200 %ptr_regoff = getelementptr i64* %p, i32 %off32
201 %val_regoff = load atomic i64* %ptr_regoff unordered, align 8
202 %tot1 = add i64 %val_unsigned, %val_regoff
203 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
204 ; CHECK: ldr {{x[0-9]+}}, [x0, x1, sxtw #3]
206 %ptr_unscaled = getelementptr i64* %p, i32 -32
207 %val_unscaled = load atomic i64* %ptr_unscaled monotonic, align 8
208 %tot2 = add i64 %tot1, %val_unscaled
209 ; CHECK: ldur {{x[0-9]+}}, [x0, #-256]
211 %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
212 %val_random = load atomic i64* %ptr_random unordered, align 8
213 %tot3 = add i64 %tot2, %val_random
214 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
215 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
221 define void @atomc_store(i32* %p) {
222 store atomic i32 4, i32* %p seq_cst, align 4
224 ; CHECK-LABEL: atomc_store:
228 define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
229 ; CHECK-LABEL: atomic_store_relaxed_8:
230 %ptr_unsigned = getelementptr i8* %p, i32 4095
231 store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
232 ; CHECK: strb {{w[0-9]+}}, [x0, #4095]
234 %ptr_regoff = getelementptr i8* %p, i32 %off32
235 store atomic i8 %val, i8* %ptr_regoff unordered, align 1
236 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
237 ; CHECK: strb {{w[0-9]+}}, [x0, x1, sxtw]
239 %ptr_unscaled = getelementptr i8* %p, i32 -256
240 store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1
241 ; CHECK: sturb {{w[0-9]+}}, [x0, #-256]
243 %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
244 store atomic i8 %val, i8* %ptr_random unordered, align 1
245 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
246 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
251 define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
252 ; CHECK-LABEL: atomic_store_relaxed_16:
253 %ptr_unsigned = getelementptr i16* %p, i32 4095
254 store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
255 ; CHECK: strh {{w[0-9]+}}, [x0, #8190]
257 %ptr_regoff = getelementptr i16* %p, i32 %off32
258 store atomic i16 %val, i16* %ptr_regoff unordered, align 2
259 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
260 ; CHECK: strh {{w[0-9]+}}, [x0, x1, sxtw #1]
262 %ptr_unscaled = getelementptr i16* %p, i32 -128
263 store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2
264 ; CHECK: sturh {{w[0-9]+}}, [x0, #-256]
266 %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
267 store atomic i16 %val, i16* %ptr_random unordered, align 2
268 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
269 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
274 define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
275 ; CHECK-LABEL: atomic_store_relaxed_32:
276 %ptr_unsigned = getelementptr i32* %p, i32 4095
277 store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
278 ; CHECK: str {{w[0-9]+}}, [x0, #16380]
280 %ptr_regoff = getelementptr i32* %p, i32 %off32
281 store atomic i32 %val, i32* %ptr_regoff unordered, align 4
282 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
283 ; CHECK: str {{w[0-9]+}}, [x0, x1, sxtw #2]
285 %ptr_unscaled = getelementptr i32* %p, i32 -64
286 store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4
287 ; CHECK: stur {{w[0-9]+}}, [x0, #-256]
289 %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
290 store atomic i32 %val, i32* %ptr_random unordered, align 4
291 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
292 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
297 define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
298 ; CHECK-LABEL: atomic_store_relaxed_64:
299 %ptr_unsigned = getelementptr i64* %p, i32 4095
300 store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
301 ; CHECK: str {{x[0-9]+}}, [x0, #32760]
303 %ptr_regoff = getelementptr i64* %p, i32 %off32
304 store atomic i64 %val, i64* %ptr_regoff unordered, align 8
305 ; FIXME: syntax is incorrect: "sxtw" should not be able to go with an x-reg.
306 ; CHECK: str {{x[0-9]+}}, [x0, x1, sxtw #3]
308 %ptr_unscaled = getelementptr i64* %p, i32 -32
309 store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8
310 ; CHECK: stur {{x[0-9]+}}, [x0, #-256]
312 %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
313 store atomic i64 %val, i64* %ptr_random unordered, align 8
314 ; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936
315 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
323 %"class.X::Atomic" = type { %struct.x_atomic_t }
324 %struct.x_atomic_t = type { i32 }
326 @counter = external hidden global %"class.X::Atomic", align 4
328 define i32 @next_id() nounwind optsize ssp align 2 {
330 %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
331 %add.i = add i32 %0, 1
332 %tobool = icmp eq i32 %add.i, 0
333 br i1 %tobool, label %if.else, label %return
335 if.else: ; preds = %entry
336 %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
337 %add.i2 = add i32 %1, 1
340 return: ; preds = %if.else, %entry
341 %retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]