1 ; RUN: llc < %s -march=arm64 -verify-machineinstrs -mcpu=cyclone | FileCheck %s
3 define i32 @val_compare_and_swap(i32* %p) {
4 ; CHECK-LABEL: val_compare_and_swap:
5 ; CHECK: orr [[NEWVAL_REG:w[0-9]+]], wzr, #0x4
6 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
7 ; CHECK: ldaxr [[RESULT:w[0-9]+]], [x0]
8 ; CHECK: cmp [[RESULT]], #7
9 ; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
10 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[NEWVAL_REG]], [x0]
11 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
13 %val = cmpxchg i32* %p, i32 7, i32 4 acquire acquire
17 define i64 @val_compare_and_swap_64(i64* %p) {
18 ; CHECK-LABEL: val_compare_and_swap_64:
19 ; CHECK: orr w[[NEWVAL_REG:[0-9]+]], wzr, #0x4
20 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
21 ; CHECK: ldxr [[RESULT:x[0-9]+]], [x0]
22 ; CHECK: cmp [[RESULT]], #7
23 ; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
24 ; CHECK-NOT: stxr x[[NEWVAL_REG]], x[[NEWVAL_REG]]
25 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], x[[NEWVAL_REG]], [x0]
26 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
28 %val = cmpxchg i64* %p, i64 7, i64 4 monotonic monotonic
32 define i32 @fetch_and_nand(i32* %p) {
33 ; CHECK-LABEL: fetch_and_nand:
34 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
35 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
36 ; CHECK: and [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], #0xfffffff8
37 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
38 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
39 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
40 ; CHECK: mov x0, x[[DEST_REG]]
41 %val = atomicrmw nand i32* %p, i32 7 release
45 define i64 @fetch_and_nand_64(i64* %p) {
46 ; CHECK-LABEL: fetch_and_nand_64:
47 ; CHECK: mov x[[ADDR:[0-9]+]], x0
48 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
49 ; CHECK: ldaxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
50 ; CHECK: and [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0xfffffffffffffff8
51 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
52 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
54 %val = atomicrmw nand i64* %p, i64 7 acq_rel
58 define i32 @fetch_and_or(i32* %p) {
59 ; CHECK-LABEL: fetch_and_or:
60 ; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5
61 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
62 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
63 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
64 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
65 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
66 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
67 ; CHECK: mov x0, x[[DEST_REG]]
68 %val = atomicrmw or i32* %p, i32 5 seq_cst
72 define i64 @fetch_and_or_64(i64* %p) {
73 ; CHECK: fetch_and_or_64:
74 ; CHECK: mov x[[ADDR:[0-9]+]], x0
75 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
76 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
77 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
78 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
79 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
80 %val = atomicrmw or i64* %p, i64 7 monotonic
84 define void @acquire_fence() {
87 ; CHECK-LABEL: acquire_fence:
91 define void @release_fence() {
94 ; CHECK-LABEL: release_fence:
98 define void @seq_cst_fence() {
101 ; CHECK-LABEL: seq_cst_fence:
102 ; CHECK: dmb ish{{$}}
105 define i32 @atomic_load(i32* %p) {
106 %r = load atomic i32* %p seq_cst, align 4
108 ; CHECK-LABEL: atomic_load:
112 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
113 ; CHECK-LABEL: atomic_load_relaxed_8:
114 %ptr_unsigned = getelementptr i8* %p, i32 4095
115 %val_unsigned = load atomic i8* %ptr_unsigned monotonic, align 1
116 ; CHECK: ldrb {{w[0-9]+}}, [x0, #4095]
118 %ptr_regoff = getelementptr i8* %p, i32 %off32
119 %val_regoff = load atomic i8* %ptr_regoff unordered, align 1
120 %tot1 = add i8 %val_unsigned, %val_regoff
121 ; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw]
123 %ptr_unscaled = getelementptr i8* %p, i32 -256
124 %val_unscaled = load atomic i8* %ptr_unscaled monotonic, align 1
125 %tot2 = add i8 %tot1, %val_unscaled
126 ; CHECK: ldurb {{w[0-9]+}}, [x0, #-256]
128 %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
129 %val_random = load atomic i8* %ptr_random unordered, align 1
130 %tot3 = add i8 %tot2, %val_random
131 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
132 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
137 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
138 ; CHECK-LABEL: atomic_load_relaxed_16:
139 %ptr_unsigned = getelementptr i16* %p, i32 4095
140 %val_unsigned = load atomic i16* %ptr_unsigned monotonic, align 2
141 ; CHECK: ldrh {{w[0-9]+}}, [x0, #8190]
143 %ptr_regoff = getelementptr i16* %p, i32 %off32
144 %val_regoff = load atomic i16* %ptr_regoff unordered, align 2
145 %tot1 = add i16 %val_unsigned, %val_regoff
146 ; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1]
148 %ptr_unscaled = getelementptr i16* %p, i32 -128
149 %val_unscaled = load atomic i16* %ptr_unscaled monotonic, align 2
150 %tot2 = add i16 %tot1, %val_unscaled
151 ; CHECK: ldurh {{w[0-9]+}}, [x0, #-256]
153 %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
154 %val_random = load atomic i16* %ptr_random unordered, align 2
155 %tot3 = add i16 %tot2, %val_random
156 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
157 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
162 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
163 ; CHECK-LABEL: atomic_load_relaxed_32:
164 %ptr_unsigned = getelementptr i32* %p, i32 4095
165 %val_unsigned = load atomic i32* %ptr_unsigned monotonic, align 4
166 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
168 %ptr_regoff = getelementptr i32* %p, i32 %off32
169 %val_regoff = load atomic i32* %ptr_regoff unordered, align 4
170 %tot1 = add i32 %val_unsigned, %val_regoff
171 ; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2]
173 %ptr_unscaled = getelementptr i32* %p, i32 -64
174 %val_unscaled = load atomic i32* %ptr_unscaled monotonic, align 4
175 %tot2 = add i32 %tot1, %val_unscaled
176 ; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
178 %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
179 %val_random = load atomic i32* %ptr_random unordered, align 4
180 %tot3 = add i32 %tot2, %val_random
181 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
182 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
187 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
188 ; CHECK-LABEL: atomic_load_relaxed_64:
189 %ptr_unsigned = getelementptr i64* %p, i32 4095
190 %val_unsigned = load atomic i64* %ptr_unsigned monotonic, align 8
191 ; CHECK: ldr {{x[0-9]+}}, [x0, #32760]
193 %ptr_regoff = getelementptr i64* %p, i32 %off32
194 %val_regoff = load atomic i64* %ptr_regoff unordered, align 8
195 %tot1 = add i64 %val_unsigned, %val_regoff
196 ; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3]
198 %ptr_unscaled = getelementptr i64* %p, i32 -32
199 %val_unscaled = load atomic i64* %ptr_unscaled monotonic, align 8
200 %tot2 = add i64 %tot1, %val_unscaled
201 ; CHECK: ldur {{x[0-9]+}}, [x0, #-256]
203 %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
204 %val_random = load atomic i64* %ptr_random unordered, align 8
205 %tot3 = add i64 %tot2, %val_random
206 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
207 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
213 define void @atomc_store(i32* %p) {
214 store atomic i32 4, i32* %p seq_cst, align 4
216 ; CHECK-LABEL: atomc_store:
220 define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
221 ; CHECK-LABEL: atomic_store_relaxed_8:
222 %ptr_unsigned = getelementptr i8* %p, i32 4095
223 store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
224 ; CHECK: strb {{w[0-9]+}}, [x0, #4095]
226 %ptr_regoff = getelementptr i8* %p, i32 %off32
227 store atomic i8 %val, i8* %ptr_regoff unordered, align 1
228 ; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw]
230 %ptr_unscaled = getelementptr i8* %p, i32 -256
231 store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1
232 ; CHECK: sturb {{w[0-9]+}}, [x0, #-256]
234 %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
235 store atomic i8 %val, i8* %ptr_random unordered, align 1
236 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
237 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
242 define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
243 ; CHECK-LABEL: atomic_store_relaxed_16:
244 %ptr_unsigned = getelementptr i16* %p, i32 4095
245 store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
246 ; CHECK: strh {{w[0-9]+}}, [x0, #8190]
248 %ptr_regoff = getelementptr i16* %p, i32 %off32
249 store atomic i16 %val, i16* %ptr_regoff unordered, align 2
250 ; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1]
252 %ptr_unscaled = getelementptr i16* %p, i32 -128
253 store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2
254 ; CHECK: sturh {{w[0-9]+}}, [x0, #-256]
256 %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
257 store atomic i16 %val, i16* %ptr_random unordered, align 2
258 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
259 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
264 define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
265 ; CHECK-LABEL: atomic_store_relaxed_32:
266 %ptr_unsigned = getelementptr i32* %p, i32 4095
267 store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
268 ; CHECK: str {{w[0-9]+}}, [x0, #16380]
270 %ptr_regoff = getelementptr i32* %p, i32 %off32
271 store atomic i32 %val, i32* %ptr_regoff unordered, align 4
272 ; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2]
274 %ptr_unscaled = getelementptr i32* %p, i32 -64
275 store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4
276 ; CHECK: stur {{w[0-9]+}}, [x0, #-256]
278 %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
279 store atomic i32 %val, i32* %ptr_random unordered, align 4
280 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
281 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
286 define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
287 ; CHECK-LABEL: atomic_store_relaxed_64:
288 %ptr_unsigned = getelementptr i64* %p, i32 4095
289 store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
290 ; CHECK: str {{x[0-9]+}}, [x0, #32760]
292 %ptr_regoff = getelementptr i64* %p, i32 %off32
293 store atomic i64 %val, i64* %ptr_regoff unordered, align 8
294 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]
296 %ptr_unscaled = getelementptr i64* %p, i32 -32
297 store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8
298 ; CHECK: stur {{x[0-9]+}}, [x0, #-256]
300 %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
301 store atomic i64 %val, i64* %ptr_random unordered, align 8
302 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
303 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
311 %"class.X::Atomic" = type { %struct.x_atomic_t }
312 %struct.x_atomic_t = type { i32 }
314 @counter = external hidden global %"class.X::Atomic", align 4
316 define i32 @next_id() nounwind optsize ssp align 2 {
318 %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
319 %add.i = add i32 %0, 1
320 %tobool = icmp eq i32 %add.i, 0
321 br i1 %tobool, label %if.else, label %return
323 if.else: ; preds = %entry
324 %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
325 %add.i2 = add i32 %1, 1
328 return: ; preds = %if.else, %entry
329 %retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]