1 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
3 ;; Test various conversions.
4 define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
7 ; CHECK: sub sp, sp, #16
8 ; CHECK: strb w0, [sp, #15]
9 ; CHECK: strh w1, [sp, #12]
10 ; CHECK: str w2, [sp, #8]
14 ; CHECK: str w0, [sp, #8]
15 ; CHECK: ldr w0, [sp, #8]
16 ; CHECK: strh w0, [sp, #12]
17 ; CHECK: ldrh w0, [sp, #12]
18 ; CHECK: strb w0, [sp, #15]
19 ; CHECK: ldrb w0, [sp, #15]
21 ; CHECK: add sp, sp, #16
23 %a.addr = alloca i8, align 1
24 %b.addr = alloca i16, align 2
25 %c.addr = alloca i32, align 4
26 %d.addr = alloca i64, align 8
27 store i8 %a, i8* %a.addr, align 1
28 store i16 %b, i16* %b.addr, align 2
29 store i32 %c, i32* %c.addr, align 4
30 store i64 %d, i64* %d.addr, align 8
31 %tmp = load i64* %d.addr, align 8
32 %conv = trunc i64 %tmp to i32
33 store i32 %conv, i32* %c.addr, align 4
34 %tmp1 = load i32* %c.addr, align 4
35 %conv2 = trunc i32 %tmp1 to i16
36 store i16 %conv2, i16* %b.addr, align 2
37 %tmp3 = load i16* %b.addr, align 2
38 %conv4 = trunc i16 %tmp3 to i8
39 store i8 %conv4, i8* %a.addr, align 1
40 %tmp5 = load i8* %a.addr, align 1
41 %conv6 = zext i8 %tmp5 to i32
45 define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
48 ; CHECK: sub sp, sp, #16
49 ; CHECK: strb w0, [sp, #15]
50 ; CHECK: strh w1, [sp, #12]
51 ; CHECK: str w2, [sp, #8]
53 ; CHECK: ldrb w0, [sp, #15]
55 ; CHECK: strh w0, [sp, #12]
56 ; CHECK: ldrh w0, [sp, #12]
58 ; CHECK: str w0, [sp, #8]
59 ; CHECK: ldr w0, [sp, #8]
61 ; CHECK: ubfx x3, x3, #0, #32
63 ; CHECK: ldr x0, [sp], #16
65 %a.addr = alloca i8, align 1
66 %b.addr = alloca i16, align 2
67 %c.addr = alloca i32, align 4
68 %d.addr = alloca i64, align 8
69 store i8 %a, i8* %a.addr, align 1
70 store i16 %b, i16* %b.addr, align 2
71 store i32 %c, i32* %c.addr, align 4
72 store i64 %d, i64* %d.addr, align 8
73 %tmp = load i8* %a.addr, align 1
74 %conv = zext i8 %tmp to i16
75 store i16 %conv, i16* %b.addr, align 2
76 %tmp1 = load i16* %b.addr, align 2
77 %conv2 = zext i16 %tmp1 to i32
78 store i32 %conv2, i32* %c.addr, align 4
79 %tmp3 = load i32* %c.addr, align 4
80 %conv4 = zext i32 %tmp3 to i64
81 store i64 %conv4, i64* %d.addr, align 8
82 %tmp5 = load i64* %d.addr, align 8
86 define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
89 ; CHECK: and w0, w0, #0x1
90 %conv = zext i1 %a to i32
94 define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
97 ; CHECK: and w0, w0, #0x1
98 %conv = zext i1 %a to i64
102 define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
105 ; CHECK: sub sp, sp, #16
106 ; CHECK: strb w0, [sp, #15]
107 ; CHECK: strh w1, [sp, #12]
108 ; CHECK: str w2, [sp, #8]
109 ; CHECK: str x3, [sp]
110 ; CHECK: ldrb w0, [sp, #15]
112 ; CHECK: strh w0, [sp, #12]
113 ; CHECK: ldrh w0, [sp, #12]
115 ; CHECK: str w0, [sp, #8]
116 ; CHECK: ldr w0, [sp, #8]
119 ; CHECK: str x3, [sp]
120 ; CHECK: ldr x0, [sp], #16
122 %a.addr = alloca i8, align 1
123 %b.addr = alloca i16, align 2
124 %c.addr = alloca i32, align 4
125 %d.addr = alloca i64, align 8
126 store i8 %a, i8* %a.addr, align 1
127 store i16 %b, i16* %b.addr, align 2
128 store i32 %c, i32* %c.addr, align 4
129 store i64 %d, i64* %d.addr, align 8
130 %tmp = load i8* %a.addr, align 1
131 %conv = sext i8 %tmp to i16
132 store i16 %conv, i16* %b.addr, align 2
133 %tmp1 = load i16* %b.addr, align 2
134 %conv2 = sext i16 %tmp1 to i32
135 store i32 %conv2, i32* %c.addr, align 4
136 %tmp3 = load i32* %c.addr, align 4
137 %conv4 = sext i32 %tmp3 to i64
138 store i64 %conv4, i64* %d.addr, align 8
139 %tmp5 = load i64* %d.addr, align 8
143 ; Test sext i8 to i64
145 define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
146 ; CHECK-LABEL: sext_i8_i64:
147 ; CHECK: mov x[[TMP:[0-9]+]], x0
148 ; CHECK: sxtb x0, w[[TMP]]
149 %big = sext i8 %in to i64
153 define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
154 ; CHECK-LABEL: sext_i16_i64:
155 ; CHECK: mov x[[TMP:[0-9]+]], x0
156 ; CHECK: sxth x0, w[[TMP]]
157 %big = sext i16 %in to i64
161 ; Test sext i1 to i32
162 define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
165 ; CHECK: sbfx w0, w0, #0, #1
166 %conv = sext i1 %a to i32
170 ; Test sext i1 to i16
171 define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
174 ; CHECK: sbfx w0, w0, #0, #1
175 %conv = sext i1 %a to i16
180 define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
183 ; CHECK: sbfx w0, w0, #0, #1
184 %conv = sext i1 %a to i8
189 define double @fpext_(float %a) nounwind ssp {
193 %conv = fpext float %a to double
198 define float @fptrunc_(double %a) nounwind ssp {
202 %conv = fptrunc double %a to float
207 define i32 @fptosi_ws(float %a) nounwind ssp {
210 ; CHECK: fcvtzs w0, s0
211 %conv = fptosi float %a to i32
216 define i32 @fptosi_wd(double %a) nounwind ssp {
219 ; CHECK: fcvtzs w0, d0
220 %conv = fptosi double %a to i32
225 define i32 @fptoui_ws(float %a) nounwind ssp {
228 ; CHECK: fcvtzu w0, s0
229 %conv = fptoui float %a to i32
234 define i32 @fptoui_wd(double %a) nounwind ssp {
237 ; CHECK: fcvtzu w0, d0
238 %conv = fptoui double %a to i32
243 define float @sitofp_sw_i1(i1 %a) nounwind ssp {
245 ; CHECK: sitofp_sw_i1
246 ; CHECK: sbfx w0, w0, #0, #1
247 ; CHECK: scvtf s0, w0
248 %conv = sitofp i1 %a to float
253 define float @sitofp_sw_i8(i8 %a) nounwind ssp {
255 ; CHECK: sitofp_sw_i8
257 ; CHECK: scvtf s0, w0
258 %conv = sitofp i8 %a to float
263 define float @sitofp_sw_i16(i16 %a) nounwind ssp {
265 ; CHECK: sitofp_sw_i16
267 ; CHECK: scvtf s0, w0
268 %conv = sitofp i16 %a to float
273 define float @sitofp_sw(i32 %a) nounwind ssp {
276 ; CHECK: scvtf s0, w0
277 %conv = sitofp i32 %a to float
282 define float @sitofp_sx(i64 %a) nounwind ssp {
285 ; CHECK: scvtf s0, x0
286 %conv = sitofp i64 %a to float
291 define double @sitofp_dw(i32 %a) nounwind ssp {
294 ; CHECK: scvtf d0, w0
295 %conv = sitofp i32 %a to double
300 define double @sitofp_dx(i64 %a) nounwind ssp {
303 ; CHECK: scvtf d0, x0
304 %conv = sitofp i64 %a to double
309 define float @uitofp_sw_i1(i1 %a) nounwind ssp {
311 ; CHECK: uitofp_sw_i1
312 ; CHECK: and w0, w0, #0x1
313 ; CHECK: ucvtf s0, w0
314 %conv = uitofp i1 %a to float
319 define float @uitofp_sw_i8(i8 %a) nounwind ssp {
321 ; CHECK: uitofp_sw_i8
323 ; CHECK: ucvtf s0, w0
324 %conv = uitofp i8 %a to float
329 define float @uitofp_sw_i16(i16 %a) nounwind ssp {
331 ; CHECK: uitofp_sw_i16
333 ; CHECK: ucvtf s0, w0
334 %conv = uitofp i16 %a to float
339 define float @uitofp_sw(i32 %a) nounwind ssp {
342 ; CHECK: ucvtf s0, w0
343 %conv = uitofp i32 %a to float
348 define float @uitofp_sx(i64 %a) nounwind ssp {
351 ; CHECK: ucvtf s0, x0
352 %conv = uitofp i64 %a to float
357 define double @uitofp_dw(i32 %a) nounwind ssp {
360 ; CHECK: ucvtf d0, w0
361 %conv = uitofp i32 %a to double
366 define double @uitofp_dx(i64 %a) nounwind ssp {
369 ; CHECK: ucvtf d0, x0
370 %conv = uitofp i64 %a to double
374 define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
376 ; CHECK: i64_trunc_i32
378 %conv = trunc i64 %a to i32
382 define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
384 ; CHECK: i64_trunc_i16
385 ; CHECK: mov x[[REG:[0-9]+]], x0
386 ; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
387 ; CHECK: uxth w0, [[REG2]]
388 %conv = trunc i64 %a to i16
392 define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
394 ; CHECK: i64_trunc_i8
395 ; CHECK: mov x[[REG:[0-9]+]], x0
396 ; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
397 ; CHECK: uxtb w0, [[REG2]]
398 %conv = trunc i64 %a to i8
402 define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
404 ; CHECK: i64_trunc_i1
405 ; CHECK: mov x[[REG:[0-9]+]], x0
406 ; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
407 ; CHECK: and w0, [[REG2]], #0x1
408 %conv = trunc i64 %a to i1
413 define void @stack_trunc() nounwind {
415 ; CHECK: sub sp, sp, #16
416 ; CHECK: ldr [[REG:x[0-9]+]], [sp]
417 ; CHECK: mov x[[REG2:[0-9]+]], [[REG]]
418 ; CHECK: and [[REG3:w[0-9]+]], w[[REG2]], #0xff
419 ; CHECK: strb [[REG3]], [sp, #15]
420 ; CHECK: add sp, sp, #16
421 %a = alloca i8, align 1
422 %b = alloca i64, align 8
423 %c = load i64* %b, align 8
424 %d = trunc i64 %c to i8
425 store i8 %d, i8* %a, align 1
429 define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
430 ; CHECK-LABEL: zext_i8_i64:
431 ; CHECK: mov x[[TMP:[0-9]+]], x0
432 ; CHECK: ubfx x0, x[[TMP]], #0, #8
433 %big = zext i8 %in to i64
436 define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
437 ; CHECK-LABEL: zext_i16_i64:
438 ; CHECK: mov x[[TMP:[0-9]+]], x0
439 ; CHECK: ubfx x0, x[[TMP]], #0, #16
440 %big = zext i16 %in to i64