1 ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
4 define i1 @fcmp_float1(float %a) nounwind ssp {
8 ; CHECK: csinc w0, wzr, wzr, eq
9 %cmp = fcmp une float %a, 0.000000e+00
13 define i1 @fcmp_float2(float %a, float %b) nounwind ssp {
17 ; CHECK: csinc w0, wzr, wzr, eq
18 %cmp = fcmp une float %a, %b
22 define i1 @fcmp_double1(double %a) nounwind ssp {
24 ; CHECK: @fcmp_double1
25 ; CHECK: fcmp d0, #0.0
26 ; CHECK: csinc w0, wzr, wzr, eq
27 %cmp = fcmp une double %a, 0.000000e+00
31 define i1 @fcmp_double2(double %a, double %b) nounwind ssp {
33 ; CHECK: @fcmp_double2
35 ; CHECK: csinc w0, wzr, wzr, eq
36 %cmp = fcmp une double %a, %b
40 ; Check each fcmp condition
41 define float @fcmp_oeq(float %a, float %b) nounwind ssp {
44 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne
45 %cmp = fcmp oeq float %a, %b
46 %conv = uitofp i1 %cmp to float
50 define float @fcmp_ogt(float %a, float %b) nounwind ssp {
53 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le
54 %cmp = fcmp ogt float %a, %b
55 %conv = uitofp i1 %cmp to float
59 define float @fcmp_oge(float %a, float %b) nounwind ssp {
62 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt
63 %cmp = fcmp oge float %a, %b
64 %conv = uitofp i1 %cmp to float
68 define float @fcmp_olt(float %a, float %b) nounwind ssp {
71 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl
72 %cmp = fcmp olt float %a, %b
73 %conv = uitofp i1 %cmp to float
77 define float @fcmp_ole(float %a, float %b) nounwind ssp {
80 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi
81 %cmp = fcmp ole float %a, %b
82 %conv = uitofp i1 %cmp to float
86 define float @fcmp_ord(float %a, float %b) nounwind ssp {
89 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vs
90 %cmp = fcmp ord float %a, %b
91 %conv = uitofp i1 %cmp to float
95 define float @fcmp_uno(float %a, float %b) nounwind ssp {
98 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vc
99 %cmp = fcmp uno float %a, %b
100 %conv = uitofp i1 %cmp to float
104 define float @fcmp_ugt(float %a, float %b) nounwind ssp {
107 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ls
108 %cmp = fcmp ugt float %a, %b
109 %conv = uitofp i1 %cmp to float
113 define float @fcmp_uge(float %a, float %b) nounwind ssp {
116 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, mi
117 %cmp = fcmp uge float %a, %b
118 %conv = uitofp i1 %cmp to float
122 define float @fcmp_ult(float %a, float %b) nounwind ssp {
125 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ge
126 %cmp = fcmp ult float %a, %b
127 %conv = uitofp i1 %cmp to float
131 define float @fcmp_ule(float %a, float %b) nounwind ssp {
134 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt
135 %cmp = fcmp ule float %a, %b
136 %conv = uitofp i1 %cmp to float
140 define float @fcmp_une(float %a, float %b) nounwind ssp {
143 ; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
144 %cmp = fcmp une float %a, %b
145 %conv = uitofp i1 %cmp to float
149 ; Possible opportunity for improvement. See comment in
150 ; ARM64TargetLowering::LowerSETCC()
151 define float @fcmp_one(float %a, float %b) nounwind ssp {
155 ; csel w1, w0, wzr, mi
156 ; csel w0, w0, wzr, gt
157 %cmp = fcmp one float %a, %b
158 %conv = uitofp i1 %cmp to float
162 ; Possible opportunity for improvement. See comment in
163 ; ARM64TargetLowering::LowerSETCC()
164 define float @fcmp_ueq(float %a, float %b) nounwind ssp {
168 ; CHECK: csel [[REG1:w[0-9]]], [[REG2:w[0-9]+]], wzr, eq
169 ; CHECK: csel {{w[0-9]+}}, [[REG2]], [[REG1]], vs
170 %cmp = fcmp ueq float %a, %b
171 %conv = uitofp i1 %cmp to float