1 ; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
2 ; ModuleID = 'arm64_vecCmpBr.c'
3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
4 target triple = "arm64-apple-ios3.0.0"
7 define i32 @anyZero64(<4 x i16> %a) #0 {
9 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
10 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
11 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
15 %0 = bitcast <4 x i16> %a to <8 x i8>
16 %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
17 %1 = trunc i32 %vminv.i to i8
18 %tobool = icmp eq i8 %1, 0
19 br i1 %tobool, label %if.then, label %return
21 if.then: ; preds = %entry
22 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
25 return: ; preds = %entry, %if.then
26 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
30 declare i32 @bar(...) #1
32 define i32 @anyZero128(<8 x i16> %a) #0 {
34 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
35 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
36 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
41 %0 = bitcast <8 x i16> %a to <16 x i8>
42 %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
43 %1 = trunc i32 %vminv.i to i8
44 %tobool = icmp eq i8 %1, 0
45 br i1 %tobool, label %if.then, label %return
47 if.then: ; preds = %entry
48 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
51 return: ; preds = %entry, %if.then
52 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
56 define i32 @anyNonZero64(<4 x i16> %a) #0 {
57 ; CHECK: _anyNonZero64:
58 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
59 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
60 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
62 ; CHECK-NEXT: movz w0, #0
65 %0 = bitcast <4 x i16> %a to <8 x i8>
66 %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
67 %1 = trunc i32 %vmaxv.i to i8
68 %tobool = icmp eq i8 %1, 0
69 br i1 %tobool, label %return, label %if.then
71 if.then: ; preds = %entry
72 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
75 return: ; preds = %entry, %if.then
76 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
80 define i32 @anyNonZero128(<8 x i16> %a) #0 {
81 ; CHECK: _anyNonZero128:
82 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
83 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
84 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
86 ; CHECK-NEXT: movz w0, #0
88 %0 = bitcast <8 x i16> %a to <16 x i8>
89 %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
90 %1 = trunc i32 %vmaxv.i to i8
91 %tobool = icmp eq i8 %1, 0
92 br i1 %tobool, label %return, label %if.then
94 if.then: ; preds = %entry
95 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
98 return: ; preds = %entry, %if.then
99 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
103 define i32 @allZero64(<4 x i16> %a) #0 {
105 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
106 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
107 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
111 %0 = bitcast <4 x i16> %a to <8 x i8>
112 %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
113 %1 = trunc i32 %vmaxv.i to i8
114 %tobool = icmp eq i8 %1, 0
115 br i1 %tobool, label %if.then, label %return
117 if.then: ; preds = %entry
118 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
121 return: ; preds = %entry, %if.then
122 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
126 define i32 @allZero128(<8 x i16> %a) #0 {
127 ; CHECK: _allZero128:
128 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
129 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
130 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
134 %0 = bitcast <8 x i16> %a to <16 x i8>
135 %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
136 %1 = trunc i32 %vmaxv.i to i8
137 %tobool = icmp eq i8 %1, 0
138 br i1 %tobool, label %if.then, label %return
140 if.then: ; preds = %entry
141 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
144 return: ; preds = %entry, %if.then
145 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
149 define i32 @allNonZero64(<4 x i16> %a) #0 {
150 ; CHECK: _allNonZero64:
151 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
152 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
153 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
155 ; CHECK-NEXT: movz w0, #0
157 %0 = bitcast <4 x i16> %a to <8 x i8>
158 %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
159 %1 = trunc i32 %vminv.i to i8
160 %tobool = icmp eq i8 %1, 0
161 br i1 %tobool, label %return, label %if.then
163 if.then: ; preds = %entry
164 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
167 return: ; preds = %entry, %if.then
168 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
172 define i32 @allNonZero128(<8 x i16> %a) #0 {
173 ; CHECK: _allNonZero128:
174 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
175 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
176 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
178 ; CHECK-NEXT: movz w0, #0
180 %0 = bitcast <8 x i16> %a to <16 x i8>
181 %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
182 %1 = trunc i32 %vminv.i to i8
183 %tobool = icmp eq i8 %1, 0
184 br i1 %tobool, label %return, label %if.then
186 if.then: ; preds = %entry
187 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
190 return: ; preds = %entry, %if.then
191 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
195 declare i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8>) #2
197 declare i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8>) #2
199 declare i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8>) #2
201 declare i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8>) #2
203 attributes #0 = { nounwind ssp "target-cpu"="cyclone" }
204 attributes #1 = { "target-cpu"="cyclone" }
205 attributes #2 = { nounwind readnone }
206 attributes #3 = { nounwind }
207 attributes #4 = { nobuiltin nounwind }