1 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
2 ; RUN: grep and %t1.s | count 232
3 ; RUN: grep andc %t1.s | count 85
4 ; RUN: grep andi %t1.s | count 36
5 ; RUN: grep andhi %t1.s | count 30
6 ; RUN: grep andbi %t1.s | count 4
7 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
10 ; AND instruction generation:
11 define <4 x i32> @and_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
12 %A = and <4 x i32> %arg1, %arg2
16 define <4 x i32> @and_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
17 %A = and <4 x i32> %arg2, %arg1
21 define <8 x i16> @and_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
22 %A = and <8 x i16> %arg1, %arg2
26 define <8 x i16> @and_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
27 %A = and <8 x i16> %arg2, %arg1
31 define <16 x i8> @and_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
32 %A = and <16 x i8> %arg2, %arg1
36 define <16 x i8> @and_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
37 %A = and <16 x i8> %arg1, %arg2
41 define i32 @and_i32_1(i32 %arg1, i32 %arg2) {
42 %A = and i32 %arg2, %arg1
46 define i32 @and_i32_2(i32 %arg1, i32 %arg2) {
47 %A = and i32 %arg1, %arg2
51 define i16 @and_i16_1(i16 %arg1, i16 %arg2) {
52 %A = and i16 %arg2, %arg1
56 define i16 @and_i16_2(i16 %arg1, i16 %arg2) {
57 %A = and i16 %arg1, %arg2
61 define i8 @and_i8_1(i8 %arg1, i8 %arg2) {
62 %A = and i8 %arg2, %arg1
66 define i8 @and_i8_2(i8 %arg1, i8 %arg2) {
67 %A = and i8 %arg1, %arg2
71 ; ANDC instruction generation:
72 define <4 x i32> @andc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
73 %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
74 %B = and <4 x i32> %arg1, %A
78 define <4 x i32> @andc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
79 %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
80 %B = and <4 x i32> %arg2, %A
84 define <4 x i32> @andc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
85 %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
86 %B = and <4 x i32> %A, %arg2
90 define <8 x i16> @andc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
91 %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
92 i16 -1, i16 -1, i16 -1, i16 -1 >
93 %B = and <8 x i16> %arg1, %A
97 define <8 x i16> @andc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
98 %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1,
99 i16 -1, i16 -1, i16 -1, i16 -1 >
100 %B = and <8 x i16> %arg2, %A
104 define <16 x i8> @andc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
105 %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
106 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
107 i8 -1, i8 -1, i8 -1, i8 -1 >
108 %B = and <16 x i8> %arg2, %A
112 define <16 x i8> @andc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
113 %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
114 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
115 i8 -1, i8 -1, i8 -1, i8 -1 >
116 %B = and <16 x i8> %arg1, %A
120 define <16 x i8> @andc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) {
121 %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
122 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
123 i8 -1, i8 -1, i8 -1, i8 -1 >
124 %B = and <16 x i8> %A, %arg1
128 define i32 @andc_i32_1(i32 %arg1, i32 %arg2) {
129 %A = xor i32 %arg2, -1
130 %B = and i32 %A, %arg1
134 define i32 @andc_i32_2(i32 %arg1, i32 %arg2) {
135 %A = xor i32 %arg1, -1
136 %B = and i32 %A, %arg2
140 define i32 @andc_i32_3(i32 %arg1, i32 %arg2) {
141 %A = xor i32 %arg2, -1
142 %B = and i32 %arg1, %A
146 define i16 @andc_i16_1(i16 %arg1, i16 %arg2) {
147 %A = xor i16 %arg2, -1
148 %B = and i16 %A, %arg1
152 define i16 @andc_i16_2(i16 %arg1, i16 %arg2) {
153 %A = xor i16 %arg1, -1
154 %B = and i16 %A, %arg2
158 define i16 @andc_i16_3(i16 %arg1, i16 %arg2) {
159 %A = xor i16 %arg2, -1
160 %B = and i16 %arg1, %A
164 define i8 @andc_i8_1(i8 %arg1, i8 %arg2) {
165 %A = xor i8 %arg2, -1
166 %B = and i8 %A, %arg1
170 define i8 @andc_i8_2(i8 %arg1, i8 %arg2) {
171 %A = xor i8 %arg1, -1
172 %B = and i8 %A, %arg2
176 define i8 @andc_i8_3(i8 %arg1, i8 %arg2) {
177 %A = xor i8 %arg2, -1
178 %B = and i8 %arg1, %A
182 ; ANDI instruction generation (i32 data type):
183 define <4 x i32> @andi_v4i32_1(<4 x i32> %in) {
184 %tmp2 = and <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
188 define <4 x i32> @andi_v4i32_2(<4 x i32> %in) {
189 %tmp2 = and <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
193 define <4 x i32> @andi_v4i32_3(<4 x i32> %in) {
194 %tmp2 = and <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
198 define <4 x i32> @andi_v4i32_4(<4 x i32> %in) {
199 %tmp2 = and <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
203 define i32 @andi_u32(i32 zeroext %in) zeroext {
204 %tmp37 = and i32 %in, 37
208 define i32 @andi_i32(i32 signext %in) signext {
209 %tmp38 = and i32 %in, 37
213 define i32 @andi_i32_1(i32 %in) {
214 %tmp37 = and i32 %in, 37
218 ; ANDHI instruction generation (i16 data type):
219 define <8 x i16> @andhi_v8i16_1(<8 x i16> %in) {
220 %tmp2 = and <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,
221 i16 511, i16 511, i16 511, i16 511 >
225 define <8 x i16> @andhi_v8i16_2(<8 x i16> %in) {
226 %tmp2 = and <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510,
227 i16 510, i16 510, i16 510, i16 510 >
231 define <8 x i16> @andhi_v8i16_3(<8 x i16> %in) {
232 %tmp2 = and <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1,
233 i16 -1, i16 -1, i16 -1 >
237 define <8 x i16> @andhi_v8i16_4(<8 x i16> %in) {
238 %tmp2 = and <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512,
239 i16 -512, i16 -512, i16 -512, i16 -512 >
243 define i16 @andhi_u16(i16 zeroext %in) zeroext {
244 %tmp37 = and i16 %in, 37 ; <i16> [#uses=1]
248 define i16 @andhi_i16(i16 signext %in) signext {
249 %tmp38 = and i16 %in, 37 ; <i16> [#uses=1]
253 ; i8 data type (s/b ANDBI if 8-bit registers were supported):
254 define <16 x i8> @and_v16i8(<16 x i8> %in) {
255 ; ANDBI generated for vector types
256 %tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
257 i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
258 i8 42, i8 42, i8 42, i8 42 >
262 define i8 @and_u8(i8 zeroext %in) zeroext {
264 %tmp37 = and i8 %in, 37
268 define i8 @and_sext8(i8 signext %in) signext {
270 %tmp38 = and i8 %in, 37
274 define i8 @and_i8(i8 %in) {
276 %tmp38 = and i8 %in, 205