1 ; RUN: llc < %s -march=cellspu > %t1.s
2 ; RUN: grep {shlh } %t1.s | count 10
3 ; RUN: grep {shlhi } %t1.s | count 3
4 ; RUN: grep {shl } %t1.s | count 10
5 ; RUN: grep {shli } %t1.s | count 3
6 ; RUN: grep {xshw } %t1.s | count 5
7 ; RUN: grep {and } %t1.s | count 15
8 ; RUN: grep {andi } %t1.s | count 4
9 ; RUN: grep {rotmi } %t1.s | count 4
10 ; RUN: grep {rotqmbyi } %t1.s | count 1
11 ; RUN: grep {rotqmbii } %t1.s | count 2
12 ; RUN: grep {rotqmby } %t1.s | count 1
13 ; RUN: grep {rotqmbi } %t1.s | count 2
14 ; RUN: grep {rotqbyi } %t1.s | count 1
15 ; RUN: grep {rotqbii } %t1.s | count 2
16 ; RUN: grep {rotqbybi } %t1.s | count 1
17 ; RUN: grep {sfi } %t1.s | count 6
18 ; RUN: cat %t1.s | FileCheck %s
20 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
23 ; Shift left i16 via register, note that the second operand to shl is promoted
26 define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
27 %A = shl i16 %arg1, %arg2
31 define i16 @shlh_i16_2(i16 %arg1, i16 %arg2) {
32 %A = shl i16 %arg2, %arg1
36 define signext i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) {
37 %A = shl i16 %arg1, %arg2
41 define signext i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) {
42 %A = shl i16 %arg2, %arg1
46 define zeroext i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) {
47 %A = shl i16 %arg1, %arg2
51 define zeroext i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) {
52 %A = shl i16 %arg2, %arg1
56 ; Shift left i16 with immediate:
57 define i16 @shlhi_i16_1(i16 %arg1) {
58 %A = shl i16 %arg1, 12
62 ; Should not generate anything other than the return, arg1 << 0 = arg1
63 define i16 @shlhi_i16_2(i16 %arg1) {
68 define i16 @shlhi_i16_3(i16 %arg1) {
69 %A = shl i16 16383, %arg1
73 ; Should generate 0, 0 << arg1 = 0
74 define i16 @shlhi_i16_4(i16 %arg1) {
79 define signext i16 @shlhi_i16_5(i16 signext %arg1) {
80 %A = shl i16 %arg1, 12
84 ; Should not generate anything other than the return, arg1 << 0 = arg1
85 define signext i16 @shlhi_i16_6(i16 signext %arg1) {
90 define signext i16 @shlhi_i16_7(i16 signext %arg1) {
91 %A = shl i16 16383, %arg1
95 ; Should generate 0, 0 << arg1 = 0
96 define signext i16 @shlhi_i16_8(i16 signext %arg1) {
101 define zeroext i16 @shlhi_i16_9(i16 zeroext %arg1) {
102 %A = shl i16 %arg1, 12
106 ; Should not generate anything other than the return, arg1 << 0 = arg1
107 define zeroext i16 @shlhi_i16_10(i16 zeroext %arg1) {
108 %A = shl i16 %arg1, 0
112 define zeroext i16 @shlhi_i16_11(i16 zeroext %arg1) {
113 %A = shl i16 16383, %arg1
117 ; Should generate 0, 0 << arg1 = 0
118 define zeroext i16 @shlhi_i16_12(i16 zeroext %arg1) {
119 %A = shl i16 0, %arg1
123 ; Shift left i32 via register, note that the second operand to shl is promoted
126 define i32 @shl_i32_1(i32 %arg1, i32 %arg2) {
127 %A = shl i32 %arg1, %arg2
131 define i32 @shl_i32_2(i32 %arg1, i32 %arg2) {
132 %A = shl i32 %arg2, %arg1
136 define signext i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) {
137 %A = shl i32 %arg1, %arg2
141 define signext i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) {
142 %A = shl i32 %arg2, %arg1
146 define zeroext i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) {
147 %A = shl i32 %arg1, %arg2
151 define zeroext i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) {
152 %A = shl i32 %arg2, %arg1
156 ; Shift left i32 with immediate:
157 define i32 @shli_i32_1(i32 %arg1) {
158 %A = shl i32 %arg1, 12
162 ; Should not generate anything other than the return, arg1 << 0 = arg1
163 define i32 @shli_i32_2(i32 %arg1) {
164 %A = shl i32 %arg1, 0
168 define i32 @shli_i32_3(i32 %arg1) {
169 %A = shl i32 16383, %arg1
173 ; Should generate 0, 0 << arg1 = 0
174 define i32 @shli_i32_4(i32 %arg1) {
175 %A = shl i32 0, %arg1
179 define signext i32 @shli_i32_5(i32 signext %arg1) {
180 %A = shl i32 %arg1, 12
184 ; Should not generate anything other than the return, arg1 << 0 = arg1
185 define signext i32 @shli_i32_6(i32 signext %arg1) {
186 %A = shl i32 %arg1, 0
190 define signext i32 @shli_i32_7(i32 signext %arg1) {
191 %A = shl i32 16383, %arg1
195 ; Should generate 0, 0 << arg1 = 0
196 define signext i32 @shli_i32_8(i32 signext %arg1) {
197 %A = shl i32 0, %arg1
201 define zeroext i32 @shli_i32_9(i32 zeroext %arg1) {
202 %A = shl i32 %arg1, 12
206 ; Should not generate anything other than the return, arg1 << 0 = arg1
207 define zeroext i32 @shli_i32_10(i32 zeroext %arg1) {
208 %A = shl i32 %arg1, 0
212 define zeroext i32 @shli_i32_11(i32 zeroext %arg1) {
213 %A = shl i32 16383, %arg1
217 ; Should generate 0, 0 << arg1 = 0
218 define zeroext i32 @shli_i32_12(i32 zeroext %arg1) {
219 %A = shl i32 0, %arg1
225 define i64 @shl_i64_1(i64 %arg1) {
226 %A = shl i64 %arg1, 9
230 define i64 @shl_i64_2(i64 %arg1) {
231 %A = shl i64 %arg1, 3
235 define i64 @shl_i64_3(i64 %arg1, i32 %shift) {
236 %1 = zext i32 %shift to i64
237 %2 = shl i64 %arg1, %1
241 ;; i64 shift right logical (shift 0s from the right)
243 define i64 @lshr_i64_1(i64 %arg1) {
244 %1 = lshr i64 %arg1, 9
248 define i64 @lshr_i64_2(i64 %arg1) {
249 %1 = lshr i64 %arg1, 3
253 define i64 @lshr_i64_3(i64 %arg1, i32 %shift) {
254 %1 = zext i32 %shift to i64
255 %2 = lshr i64 %arg1, %1
259 ;; i64 shift right arithmetic (shift 1s from the right)
261 define i64 @ashr_i64_1(i64 %arg) {
262 %1 = ashr i64 %arg, 9
266 define i64 @ashr_i64_2(i64 %arg) {
267 %1 = ashr i64 %arg, 3
271 define i64 @ashr_i64_3(i64 %arg1, i32 %shift) {
272 %1 = zext i32 %shift to i64
273 %2 = ashr i64 %arg1, %1
277 define i32 @hi32_i64(i64 %arg) {
278 %1 = lshr i64 %arg, 32
279 %2 = trunc i64 %1 to i32
284 define i128 @test_lshr_i128( i128 %val ) {
285 ;CHECK: test_lshr_i128
290 %rv = lshr i128 %val, 64
295 define <2 x i32> @shl_v2i32(<2 x i32> %val, <2 x i32> %sh) {
298 %rv = shl <2 x i32> %val, %sh
302 define <4 x i32> @shl_v4i32(<4 x i32> %val, <4 x i32> %sh) {
305 %rv = shl <4 x i32> %val, %sh
309 define <8 x i16> @shl_v8i16(<8 x i16> %val, <8 x i16> %sh) {
312 %rv = shl <8 x i16> %val, %sh
316 define <4 x i32> @lshr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
319 %rv = lshr <4 x i32> %val, %sh
323 define <8 x i16> @lshr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
327 %rv = lshr <8 x i16> %val, %sh
331 define <4 x i32> @ashr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
334 %rv = ashr <4 x i32> %val, %sh
338 define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
342 %rv = ashr <8 x i16> %val, %sh
346 define <2 x i64> @special_const() {
347 ret <2 x i64> <i64 4294967295, i64 4294967295>