1 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
2 ; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
3 ; RUN: grep il %t1.s | count 16
4 ; RUN: grep ilhu %t1.s | count 8
5 ; RUN: grep ilh %t1.s | count 13
6 ; RUN: grep iohl %t1.s | count 7
7 ; RUN: grep lqa %t1.s | count 6
8 ; RUN: grep 24672 %t1.s | count 2
9 ; RUN: grep 16429 %t1.s | count 1
10 ; RUN: grep 63572 %t1.s | count 1
11 ; RUN: grep 4660 %t1.s | count 1
12 ; RUN: grep 22136 %t1.s | count 1
13 ; RUN: grep 43981 %t1.s | count 1
14 ; RUN: grep 61202 %t1.s | count 1
15 ; RUN: grep 16393 %t1.s | count 1
16 ; RUN: grep 8699 %t1.s | count 1
17 ; RUN: grep 21572 %t1.s | count 1
18 ; RUN: grep 11544 %t1.s | count 1
19 ; RUN: grep 1311768467750121234 %t1.s | count 1
20 ; RUN: grep lqd %t2.s | count 6
23 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
24 target triple = "spu-unknown-elf"
26 ; Vector constant load tests:
29 define <4 x i32> @v4i32_constvec() {
30 ret <4 x i32> < i32 2, i32 2, i32 2, i32 2 >
33 ; Spill to constant pool
34 define <4 x i32> @v4i32_constpool() {
35 ret <4 x i32> < i32 2, i32 1, i32 1, i32 2 >
38 ; Max negative range for IL
39 define <4 x i32> @v4i32_constvec_2() {
40 ret <4 x i32> < i32 -32768, i32 -32768, i32 -32768, i32 -32768 >
43 ; ILHU <reg>, 73 (0x49)
45 define <4 x i32> @v4i32_constvec_3() {
46 ret <4 x i32> < i32 4784128, i32 4784128,
47 i32 4784128, i32 4784128 >
50 ; ILHU <reg>, 61 (0x3d)
51 ; IOHL <reg>, 15395 (0x3c23)
52 define <4 x i32> @v4i32_constvec_4() {
53 ret <4 x i32> < i32 4013091, i32 4013091,
54 i32 4013091, i32 4013091 >
57 ; ILHU <reg>, 0x5050 (20560)
58 ; IOHL <reg>, 0x5050 (20560)
59 ; Tests for whether we expand the size of the bit pattern properly, because
60 ; this could be interpreted as an i8 pattern (0x50)
61 define <4 x i32> @v4i32_constvec_5() {
62 ret <4 x i32> < i32 1347440720, i32 1347440720,
63 i32 1347440720, i32 1347440720 >
67 define <8 x i16> @v8i16_constvec_1() {
68 ret <8 x i16> < i16 32767, i16 32767, i16 32767, i16 32767,
69 i16 32767, i16 32767, i16 32767, i16 32767 >
73 define <8 x i16> @v8i16_constvec_2() {
74 ret <8 x i16> < i16 511, i16 511, i16 511, i16 511, i16 511,
75 i16 511, i16 511, i16 511 >
79 define <8 x i16> @v8i16_constvec_3() {
80 ret <8 x i16> < i16 -512, i16 -512, i16 -512, i16 -512, i16 -512,
81 i16 -512, i16 -512, i16 -512 >
84 ; ILH <reg>, 24672 (0x6060)
85 ; Tests whether we expand the size of the bit pattern properly, because
86 ; this could be interpreted as an i8 pattern (0x60)
87 define <8 x i16> @v8i16_constvec_4() {
88 ret <8 x i16> < i16 24672, i16 24672, i16 24672, i16 24672, i16 24672,
89 i16 24672, i16 24672, i16 24672 >
92 ; ILH <reg>, 24672 (0x6060)
93 ; Tests whether we expand the size of the bit pattern properly, because
94 ; this is an i8 pattern but has to be expanded out to i16 to load it
95 ; properly into the vector register.
96 define <16 x i8> @v16i8_constvec_1() {
97 ret <16 x i8> < i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96,
98 i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96 >
101 define <4 x float> @v4f32_constvec_1() {
103 ret <4 x float> < float 0x4005BF0A80000000,
104 float 0x4005BF0A80000000,
105 float 0x4005BF0A80000000,
106 float 0x4005BF0A80000000 >
109 define <4 x float> @v4f32_constvec_2() {
111 ret <4 x float> < float 0.000000e+00,
118 define <4 x float> @v4f32_constvec_3() {
120 ret <4 x float> < float 0x4005BF0A80000000,
121 float 0x3810000000000000,
122 float 0x47EFFFFFE0000000,
123 float 0x400921FB60000000 >
126 ; 1311768467750121234 => 0x 12345678 abcdef12
131 define <2 x i64> @i64_constvec_1() {
133 ret <2 x i64> < i64 1311768467750121234,
134 i64 1311768467750121234 >
137 define <2 x i64> @i64_constvec_2() {
139 ret <2 x i64> < i64 1, i64 1311768467750121234 >
142 define <2 x double> @f64_constvec_1() {
144 ret <2 x double> < double 0x400921fb54442d18,
145 double 0xbff6a09e667f3bcd >
148 ; 0x400921fb 54442d18 ->
149 ; (ILHU 0x4009 [16393]/IOHL 0x21fb [ 8699])
150 ; (ILHU 0x5444 [21572]/IOHL 0x2d18 [11544])
151 define <2 x double> @f64_constvec_2() {
153 ret <2 x double> < double 0x400921fb54442d18,
154 double 0x400921fb54442d18 >