1 ; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
3 ; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
4 ; Hexagon crashes (PR23377)
5 ; XFAIL: arm,aarch64,hexagon
7 ; Make sure we have the correct weight attached to each successor.
8 define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
9 ; CHECK-LABEL: Machine code for function test2:
11 %conv = sext i32 %x to i64
12 switch i64 %conv, label %return [
18 ; CHECK: BB#0: derived from LLVM BB %entry
19 ; CHECK: Successors according to CFG: BB#2(64) BB#4(21)
20 ; CHECK: BB#4: derived from LLVM BB %entry
21 ; CHECK: Successors according to CFG: BB#1(10) BB#5(11)
22 ; CHECK: BB#5: derived from LLVM BB %entry
23 ; CHECK: Successors according to CFG: BB#1(4) BB#3(7)
32 %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
36 !0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}
40 define void @left_leaning_weight_balanced_tree(i32 %x) {
42 switch i32 %x, label %return [
50 bb0: tail call void @g(i32 0) br label %return
51 bb1: tail call void @g(i32 1) br label %return
52 bb2: tail call void @g(i32 2) br label %return
53 bb3: tail call void @g(i32 3) br label %return
54 bb4: tail call void @g(i32 4) br label %return
55 bb5: tail call void @g(i32 5) br label %return
58 ; Check that we set branch weights on the pivot cmp instruction correctly.
59 ; Cases {0,10,20,30} go on the left with weight 13; cases {40,50} go on the
60 ; right with weight 20.
62 ; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
63 ; CHECK: BB#0: derived from LLVM BB %entry
64 ; CHECK-NOT: Successors
65 ; CHECK: Successors according to CFG: BB#8(13) BB#9(20)
68 !1 = !{!"branch_weights",
74 i32 1, i32 10, i32 10}