1 ; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
3 ; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
6 ; Make sure we have the correct weight attached to each successor.
7 define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
8 ; CHECK: Machine code for function test2:
10 %conv = sext i32 %x to i64
11 switch i64 %conv, label %return [
17 ; CHECK: BB#0: derived from LLVM BB %entry
18 ; CHECK: Successors according to CFG: BB#2(64) BB#4(14)
19 ; CHECK: BB#4: derived from LLVM BB %entry
20 ; CHECK: Successors according to CFG: BB#1(4) BB#5(10)
21 ; CHECK: BB#5: derived from LLVM BB %entry
22 ; CHECK: Successors according to CFG: BB#1(10) BB#3(7)
31 %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
35 !0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}