1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
2 ; Check that we generate matching compare insn.
4 ; Function Attrs: nounwind
5 define i32 @neqi(i32 %argc) #0 {
7 %p = alloca i8, align 1
8 %0 = tail call i1 @llvm.hexagon.C4.cmpneqi(i32 %argc, i32 512)
9 %conv = zext i1 %0 to i8
10 store volatile i8 %conv, i8* %p, align 1
11 %p.0.p.0. = load volatile i8* %p, align 1
12 %conv1 = zext i8 %p.0.p.0. to i32
15 ; CHECK: p{{[0-3]}}{{ *}} = !cmp.eq(r{{[0-9]+}}, ##512)
17 ; Function Attrs: nounwind readnone
18 declare i1 @llvm.hexagon.C4.cmpneqi(i32, i32) #1
20 ; Function Attrs: nounwind
21 define i32 @ngti(i32 %argc) #0 {
23 %p = alloca i8, align 1
24 %0 = tail call i1 @llvm.hexagon.C4.cmpltei(i32 %argc, i32 4)
25 %conv = zext i1 %0 to i8
26 store volatile i8 %conv, i8* %p, align 1
27 %p.0.p.0. = load volatile i8* %p, align 1
28 %conv1 = zext i8 %p.0.p.0. to i32
31 ; CHECK: p{{[0-3]}}{{ *}} = !cmp.gt(r{{[0-9]+}}, #4)
33 ; Function Attrs: nounwind readnone
34 declare i1 @llvm.hexagon.C4.cmpltei(i32, i32) #1
36 ; Function Attrs: nounwind
37 define i32 @ngtui(i32 %argc) #0 {
39 %p = alloca i8, align 1
40 %0 = tail call i1 @llvm.hexagon.C4.cmplteui(i32 %argc, i32 4)
41 %conv = zext i1 %0 to i8
42 store volatile i8 %conv, i8* %p, align 1
43 %p.0.p.0. = load volatile i8* %p, align 1
44 %conv1 = zext i8 %p.0.p.0. to i32
47 ; CHECK: p{{[0-3]}}{{ *}} = !cmp.gtu(r{{[0-9]+}}, #4)
49 ; Function Attrs: nounwind readnone
50 declare i1 @llvm.hexagon.C4.cmplteui(i32, i32) #1