1 ; RUN: llc -march=hexagon < %s | FileCheck %s
2 ; Check that we generate load instruction with (base + register offset << x)
6 define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind {
7 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
10 %scevgep9 = getelementptr i32, i32* %a, i32 %tmp
11 %val = load i32, i32* %scevgep9, align 4
15 ; load unsigned half word
17 define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind {
18 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
21 %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
22 %val = load i16, i16* %scevgep9, align 2
26 ; load signed half word
28 define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind {
29 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
32 %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
33 %val = load i16, i16* %scevgep9, align 2
34 %conv = sext i16 %val to i32
40 define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind {
41 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0)
44 %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
45 %val = load i8, i8* %scevgep9, align 1
51 define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind {
52 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0)
55 %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
56 %val = load i8, i8* %scevgep9, align 1
57 %conv = sext i8 %val to i32
63 define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind {
64 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3)
67 %scevgep9 = getelementptr i64, i64* %a, i32 %tmp
68 %val = load i64, i64* %scevgep9, align 8