1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
2 ; Generate MemOps for V4 and above.
4 define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind {
6 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
7 %0 = load i8* %p, align 1, !tbaa !0
8 %conv = zext i8 %0 to i32
9 %add = add nsw i32 %conv, 5
10 %conv1 = trunc i32 %add to i8
11 store i8 %conv1, i8* %p, align 1, !tbaa !0
15 define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind {
17 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
18 %conv = zext i8 %x to i32
19 %0 = load i8* %p, align 1, !tbaa !0
20 %conv1 = zext i8 %0 to i32
21 %add = add nsw i32 %conv1, %conv
22 %conv2 = trunc i32 %add to i8
23 store i8 %conv2, i8* %p, align 1, !tbaa !0
27 define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind {
29 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
30 %conv = zext i8 %x to i32
31 %0 = load i8* %p, align 1, !tbaa !0
32 %conv1 = zext i8 %0 to i32
33 %sub = sub nsw i32 %conv1, %conv
34 %conv2 = trunc i32 %sub to i8
35 store i8 %conv2, i8* %p, align 1, !tbaa !0
39 define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind {
41 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
42 %0 = load i8* %p, align 1, !tbaa !0
44 store i8 %or3, i8* %p, align 1, !tbaa !0
48 define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind {
50 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
51 %0 = load i8* %p, align 1, !tbaa !0
53 store i8 %and3, i8* %p, align 1, !tbaa !0
57 define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind {
59 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
60 %0 = load i8* %p, align 1, !tbaa !0
61 %conv = zext i8 %0 to i32
62 %and = and i32 %conv, 223
63 %conv1 = trunc i32 %and to i8
64 store i8 %conv1, i8* %p, align 1, !tbaa !0
68 define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind {
70 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
71 %0 = load i8* %p, align 1, !tbaa !0
72 %conv = zext i8 %0 to i32
73 %or = or i32 %conv, 128
74 %conv1 = trunc i32 %or to i8
75 store i8 %conv1, i8* %p, align 1, !tbaa !0
79 define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
81 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
82 %add.ptr = getelementptr inbounds i8* %p, i32 %i
83 %0 = load i8* %add.ptr, align 1, !tbaa !0
84 %conv = zext i8 %0 to i32
85 %add = add nsw i32 %conv, 5
86 %conv1 = trunc i32 %add to i8
87 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
91 define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
93 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
94 %conv = zext i8 %x to i32
95 %add.ptr = getelementptr inbounds i8* %p, i32 %i
96 %0 = load i8* %add.ptr, align 1, !tbaa !0
97 %conv1 = zext i8 %0 to i32
98 %add = add nsw i32 %conv1, %conv
99 %conv2 = trunc i32 %add to i8
100 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
104 define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
106 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
107 %conv = zext i8 %x to i32
108 %add.ptr = getelementptr inbounds i8* %p, i32 %i
109 %0 = load i8* %add.ptr, align 1, !tbaa !0
110 %conv1 = zext i8 %0 to i32
111 %sub = sub nsw i32 %conv1, %conv
112 %conv2 = trunc i32 %sub to i8
113 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
117 define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
119 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
120 %add.ptr = getelementptr inbounds i8* %p, i32 %i
121 %0 = load i8* %add.ptr, align 1, !tbaa !0
123 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0
127 define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
129 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
130 %add.ptr = getelementptr inbounds i8* %p, i32 %i
131 %0 = load i8* %add.ptr, align 1, !tbaa !0
132 %and3 = and i8 %0, %x
133 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0
137 define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
139 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
140 %add.ptr = getelementptr inbounds i8* %p, i32 %i
141 %0 = load i8* %add.ptr, align 1, !tbaa !0
142 %conv = zext i8 %0 to i32
143 %and = and i32 %conv, 223
144 %conv1 = trunc i32 %and to i8
145 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
149 define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
151 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
152 %add.ptr = getelementptr inbounds i8* %p, i32 %i
153 %0 = load i8* %add.ptr, align 1, !tbaa !0
154 %conv = zext i8 %0 to i32
155 %or = or i32 %conv, 128
156 %conv1 = trunc i32 %or to i8
157 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
161 define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind {
163 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
164 %add.ptr = getelementptr inbounds i8* %p, i32 5
165 %0 = load i8* %add.ptr, align 1, !tbaa !0
166 %conv = zext i8 %0 to i32
167 %add = add nsw i32 %conv, 5
168 %conv1 = trunc i32 %add to i8
169 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
173 define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
175 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
176 %conv = zext i8 %x to i32
177 %add.ptr = getelementptr inbounds i8* %p, i32 5
178 %0 = load i8* %add.ptr, align 1, !tbaa !0
179 %conv1 = zext i8 %0 to i32
180 %add = add nsw i32 %conv1, %conv
181 %conv2 = trunc i32 %add to i8
182 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
186 define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
188 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
189 %conv = zext i8 %x to i32
190 %add.ptr = getelementptr inbounds i8* %p, i32 5
191 %0 = load i8* %add.ptr, align 1, !tbaa !0
192 %conv1 = zext i8 %0 to i32
193 %sub = sub nsw i32 %conv1, %conv
194 %conv2 = trunc i32 %sub to i8
195 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
199 define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
201 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
202 %add.ptr = getelementptr inbounds i8* %p, i32 5
203 %0 = load i8* %add.ptr, align 1, !tbaa !0
205 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0
209 define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
211 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
212 %add.ptr = getelementptr inbounds i8* %p, i32 5
213 %0 = load i8* %add.ptr, align 1, !tbaa !0
214 %and3 = and i8 %0, %x
215 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0
219 define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind {
221 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
222 %add.ptr = getelementptr inbounds i8* %p, i32 5
223 %0 = load i8* %add.ptr, align 1, !tbaa !0
224 %conv = zext i8 %0 to i32
225 %and = and i32 %conv, 223
226 %conv1 = trunc i32 %and to i8
227 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
231 define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind {
233 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
234 %add.ptr = getelementptr inbounds i8* %p, i32 5
235 %0 = load i8* %add.ptr, align 1, !tbaa !0
236 %conv = zext i8 %0 to i32
237 %or = or i32 %conv, 128
238 %conv1 = trunc i32 %or to i8
239 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
243 define void @memop_signed_char_add5(i8* nocapture %p) nounwind {
245 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
246 %0 = load i8* %p, align 1, !tbaa !0
247 %conv2 = zext i8 %0 to i32
248 %add = add nsw i32 %conv2, 5
249 %conv1 = trunc i32 %add to i8
250 store i8 %conv1, i8* %p, align 1, !tbaa !0
254 define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind {
256 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
257 %conv4 = zext i8 %x to i32
258 %0 = load i8* %p, align 1, !tbaa !0
259 %conv13 = zext i8 %0 to i32
260 %add = add nsw i32 %conv13, %conv4
261 %conv2 = trunc i32 %add to i8
262 store i8 %conv2, i8* %p, align 1, !tbaa !0
266 define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind {
268 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
269 %conv4 = zext i8 %x to i32
270 %0 = load i8* %p, align 1, !tbaa !0
271 %conv13 = zext i8 %0 to i32
272 %sub = sub nsw i32 %conv13, %conv4
273 %conv2 = trunc i32 %sub to i8
274 store i8 %conv2, i8* %p, align 1, !tbaa !0
278 define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind {
280 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
281 %0 = load i8* %p, align 1, !tbaa !0
283 store i8 %or3, i8* %p, align 1, !tbaa !0
287 define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind {
289 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
290 %0 = load i8* %p, align 1, !tbaa !0
291 %and3 = and i8 %0, %x
292 store i8 %and3, i8* %p, align 1, !tbaa !0
296 define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind {
298 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
299 %0 = load i8* %p, align 1, !tbaa !0
300 %conv2 = zext i8 %0 to i32
301 %and = and i32 %conv2, 223
302 %conv1 = trunc i32 %and to i8
303 store i8 %conv1, i8* %p, align 1, !tbaa !0
307 define void @memop_signed_char_setbit(i8* nocapture %p) nounwind {
309 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
310 %0 = load i8* %p, align 1, !tbaa !0
311 %conv2 = zext i8 %0 to i32
312 %or = or i32 %conv2, 128
313 %conv1 = trunc i32 %or to i8
314 store i8 %conv1, i8* %p, align 1, !tbaa !0
318 define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
320 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
321 %add.ptr = getelementptr inbounds i8* %p, i32 %i
322 %0 = load i8* %add.ptr, align 1, !tbaa !0
323 %conv2 = zext i8 %0 to i32
324 %add = add nsw i32 %conv2, 5
325 %conv1 = trunc i32 %add to i8
326 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
330 define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
332 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
333 %conv4 = zext i8 %x to i32
334 %add.ptr = getelementptr inbounds i8* %p, i32 %i
335 %0 = load i8* %add.ptr, align 1, !tbaa !0
336 %conv13 = zext i8 %0 to i32
337 %add = add nsw i32 %conv13, %conv4
338 %conv2 = trunc i32 %add to i8
339 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
343 define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
345 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
346 %conv4 = zext i8 %x to i32
347 %add.ptr = getelementptr inbounds i8* %p, i32 %i
348 %0 = load i8* %add.ptr, align 1, !tbaa !0
349 %conv13 = zext i8 %0 to i32
350 %sub = sub nsw i32 %conv13, %conv4
351 %conv2 = trunc i32 %sub to i8
352 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
356 define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
358 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
359 %add.ptr = getelementptr inbounds i8* %p, i32 %i
360 %0 = load i8* %add.ptr, align 1, !tbaa !0
362 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0
366 define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
368 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
369 %add.ptr = getelementptr inbounds i8* %p, i32 %i
370 %0 = load i8* %add.ptr, align 1, !tbaa !0
371 %and3 = and i8 %0, %x
372 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0
376 define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
378 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
379 %add.ptr = getelementptr inbounds i8* %p, i32 %i
380 %0 = load i8* %add.ptr, align 1, !tbaa !0
381 %conv2 = zext i8 %0 to i32
382 %and = and i32 %conv2, 223
383 %conv1 = trunc i32 %and to i8
384 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
388 define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
390 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
391 %add.ptr = getelementptr inbounds i8* %p, i32 %i
392 %0 = load i8* %add.ptr, align 1, !tbaa !0
393 %conv2 = zext i8 %0 to i32
394 %or = or i32 %conv2, 128
395 %conv1 = trunc i32 %or to i8
396 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
400 define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind {
402 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
403 %add.ptr = getelementptr inbounds i8* %p, i32 5
404 %0 = load i8* %add.ptr, align 1, !tbaa !0
405 %conv2 = zext i8 %0 to i32
406 %add = add nsw i32 %conv2, 5
407 %conv1 = trunc i32 %add to i8
408 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
412 define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind {
414 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
415 %conv4 = zext i8 %x to i32
416 %add.ptr = getelementptr inbounds i8* %p, i32 5
417 %0 = load i8* %add.ptr, align 1, !tbaa !0
418 %conv13 = zext i8 %0 to i32
419 %add = add nsw i32 %conv13, %conv4
420 %conv2 = trunc i32 %add to i8
421 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
425 define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind {
427 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
428 %conv4 = zext i8 %x to i32
429 %add.ptr = getelementptr inbounds i8* %p, i32 5
430 %0 = load i8* %add.ptr, align 1, !tbaa !0
431 %conv13 = zext i8 %0 to i32
432 %sub = sub nsw i32 %conv13, %conv4
433 %conv2 = trunc i32 %sub to i8
434 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0
438 define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind {
440 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
441 %add.ptr = getelementptr inbounds i8* %p, i32 5
442 %0 = load i8* %add.ptr, align 1, !tbaa !0
444 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0
448 define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind {
450 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
451 %add.ptr = getelementptr inbounds i8* %p, i32 5
452 %0 = load i8* %add.ptr, align 1, !tbaa !0
453 %and3 = and i8 %0, %x
454 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0
458 define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind {
460 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
461 %add.ptr = getelementptr inbounds i8* %p, i32 5
462 %0 = load i8* %add.ptr, align 1, !tbaa !0
463 %conv2 = zext i8 %0 to i32
464 %and = and i32 %conv2, 223
465 %conv1 = trunc i32 %and to i8
466 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
470 define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind {
472 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
473 %add.ptr = getelementptr inbounds i8* %p, i32 5
474 %0 = load i8* %add.ptr, align 1, !tbaa !0
475 %conv2 = zext i8 %0 to i32
476 %or = or i32 %conv2, 128
477 %conv1 = trunc i32 %or to i8
478 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0
482 define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind {
484 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
485 %0 = load i16* %p, align 2, !tbaa !2
486 %conv = zext i16 %0 to i32
487 %add = add nsw i32 %conv, 5
488 %conv1 = trunc i32 %add to i16
489 store i16 %conv1, i16* %p, align 2, !tbaa !2
493 define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind {
495 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
496 %conv = zext i16 %x to i32
497 %0 = load i16* %p, align 2, !tbaa !2
498 %conv1 = zext i16 %0 to i32
499 %add = add nsw i32 %conv1, %conv
500 %conv2 = trunc i32 %add to i16
501 store i16 %conv2, i16* %p, align 2, !tbaa !2
505 define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind {
507 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
508 %conv = zext i16 %x to i32
509 %0 = load i16* %p, align 2, !tbaa !2
510 %conv1 = zext i16 %0 to i32
511 %sub = sub nsw i32 %conv1, %conv
512 %conv2 = trunc i32 %sub to i16
513 store i16 %conv2, i16* %p, align 2, !tbaa !2
517 define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind {
519 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
520 %0 = load i16* %p, align 2, !tbaa !2
522 store i16 %or3, i16* %p, align 2, !tbaa !2
526 define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind {
528 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
529 %0 = load i16* %p, align 2, !tbaa !2
530 %and3 = and i16 %0, %x
531 store i16 %and3, i16* %p, align 2, !tbaa !2
535 define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind {
537 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
538 %0 = load i16* %p, align 2, !tbaa !2
539 %conv = zext i16 %0 to i32
540 %and = and i32 %conv, 65503
541 %conv1 = trunc i32 %and to i16
542 store i16 %conv1, i16* %p, align 2, !tbaa !2
546 define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind {
548 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
549 %0 = load i16* %p, align 2, !tbaa !2
550 %conv = zext i16 %0 to i32
551 %or = or i32 %conv, 128
552 %conv1 = trunc i32 %or to i16
553 store i16 %conv1, i16* %p, align 2, !tbaa !2
557 define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
559 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
560 %add.ptr = getelementptr inbounds i16* %p, i32 %i
561 %0 = load i16* %add.ptr, align 2, !tbaa !2
562 %conv = zext i16 %0 to i32
563 %add = add nsw i32 %conv, 5
564 %conv1 = trunc i32 %add to i16
565 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
569 define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
571 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
572 %conv = zext i16 %x to i32
573 %add.ptr = getelementptr inbounds i16* %p, i32 %i
574 %0 = load i16* %add.ptr, align 2, !tbaa !2
575 %conv1 = zext i16 %0 to i32
576 %add = add nsw i32 %conv1, %conv
577 %conv2 = trunc i32 %add to i16
578 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
582 define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
584 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
585 %conv = zext i16 %x to i32
586 %add.ptr = getelementptr inbounds i16* %p, i32 %i
587 %0 = load i16* %add.ptr, align 2, !tbaa !2
588 %conv1 = zext i16 %0 to i32
589 %sub = sub nsw i32 %conv1, %conv
590 %conv2 = trunc i32 %sub to i16
591 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
595 define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
597 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
598 %add.ptr = getelementptr inbounds i16* %p, i32 %i
599 %0 = load i16* %add.ptr, align 2, !tbaa !2
601 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2
605 define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
607 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
608 %add.ptr = getelementptr inbounds i16* %p, i32 %i
609 %0 = load i16* %add.ptr, align 2, !tbaa !2
610 %and3 = and i16 %0, %x
611 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2
615 define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
617 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
618 %add.ptr = getelementptr inbounds i16* %p, i32 %i
619 %0 = load i16* %add.ptr, align 2, !tbaa !2
620 %conv = zext i16 %0 to i32
621 %and = and i32 %conv, 65503
622 %conv1 = trunc i32 %and to i16
623 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
627 define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
629 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
630 %add.ptr = getelementptr inbounds i16* %p, i32 %i
631 %0 = load i16* %add.ptr, align 2, !tbaa !2
632 %conv = zext i16 %0 to i32
633 %or = or i32 %conv, 128
634 %conv1 = trunc i32 %or to i16
635 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
639 define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind {
641 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
642 %add.ptr = getelementptr inbounds i16* %p, i32 5
643 %0 = load i16* %add.ptr, align 2, !tbaa !2
644 %conv = zext i16 %0 to i32
645 %add = add nsw i32 %conv, 5
646 %conv1 = trunc i32 %add to i16
647 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
651 define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
653 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
654 %conv = zext i16 %x to i32
655 %add.ptr = getelementptr inbounds i16* %p, i32 5
656 %0 = load i16* %add.ptr, align 2, !tbaa !2
657 %conv1 = zext i16 %0 to i32
658 %add = add nsw i32 %conv1, %conv
659 %conv2 = trunc i32 %add to i16
660 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
664 define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
666 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
667 %conv = zext i16 %x to i32
668 %add.ptr = getelementptr inbounds i16* %p, i32 5
669 %0 = load i16* %add.ptr, align 2, !tbaa !2
670 %conv1 = zext i16 %0 to i32
671 %sub = sub nsw i32 %conv1, %conv
672 %conv2 = trunc i32 %sub to i16
673 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
677 define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
679 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
680 %add.ptr = getelementptr inbounds i16* %p, i32 5
681 %0 = load i16* %add.ptr, align 2, !tbaa !2
683 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2
687 define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
689 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
690 %add.ptr = getelementptr inbounds i16* %p, i32 5
691 %0 = load i16* %add.ptr, align 2, !tbaa !2
692 %and3 = and i16 %0, %x
693 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2
697 define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind {
699 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
700 %add.ptr = getelementptr inbounds i16* %p, i32 5
701 %0 = load i16* %add.ptr, align 2, !tbaa !2
702 %conv = zext i16 %0 to i32
703 %and = and i32 %conv, 65503
704 %conv1 = trunc i32 %and to i16
705 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
709 define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind {
711 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
712 %add.ptr = getelementptr inbounds i16* %p, i32 5
713 %0 = load i16* %add.ptr, align 2, !tbaa !2
714 %conv = zext i16 %0 to i32
715 %or = or i32 %conv, 128
716 %conv1 = trunc i32 %or to i16
717 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
721 define void @memop_signed_short_add5(i16* nocapture %p) nounwind {
723 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
724 %0 = load i16* %p, align 2, !tbaa !2
725 %conv2 = zext i16 %0 to i32
726 %add = add nsw i32 %conv2, 5
727 %conv1 = trunc i32 %add to i16
728 store i16 %conv1, i16* %p, align 2, !tbaa !2
732 define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind {
734 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
735 %conv4 = zext i16 %x to i32
736 %0 = load i16* %p, align 2, !tbaa !2
737 %conv13 = zext i16 %0 to i32
738 %add = add nsw i32 %conv13, %conv4
739 %conv2 = trunc i32 %add to i16
740 store i16 %conv2, i16* %p, align 2, !tbaa !2
744 define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind {
746 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
747 %conv4 = zext i16 %x to i32
748 %0 = load i16* %p, align 2, !tbaa !2
749 %conv13 = zext i16 %0 to i32
750 %sub = sub nsw i32 %conv13, %conv4
751 %conv2 = trunc i32 %sub to i16
752 store i16 %conv2, i16* %p, align 2, !tbaa !2
756 define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind {
758 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
759 %0 = load i16* %p, align 2, !tbaa !2
761 store i16 %or3, i16* %p, align 2, !tbaa !2
765 define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind {
767 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
768 %0 = load i16* %p, align 2, !tbaa !2
769 %and3 = and i16 %0, %x
770 store i16 %and3, i16* %p, align 2, !tbaa !2
774 define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind {
776 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
777 %0 = load i16* %p, align 2, !tbaa !2
778 %conv2 = zext i16 %0 to i32
779 %and = and i32 %conv2, 65503
780 %conv1 = trunc i32 %and to i16
781 store i16 %conv1, i16* %p, align 2, !tbaa !2
785 define void @memop_signed_short_setbit(i16* nocapture %p) nounwind {
787 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
788 %0 = load i16* %p, align 2, !tbaa !2
789 %conv2 = zext i16 %0 to i32
790 %or = or i32 %conv2, 128
791 %conv1 = trunc i32 %or to i16
792 store i16 %conv1, i16* %p, align 2, !tbaa !2
796 define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
798 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
799 %add.ptr = getelementptr inbounds i16* %p, i32 %i
800 %0 = load i16* %add.ptr, align 2, !tbaa !2
801 %conv2 = zext i16 %0 to i32
802 %add = add nsw i32 %conv2, 5
803 %conv1 = trunc i32 %add to i16
804 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
808 define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
810 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
811 %conv4 = zext i16 %x to i32
812 %add.ptr = getelementptr inbounds i16* %p, i32 %i
813 %0 = load i16* %add.ptr, align 2, !tbaa !2
814 %conv13 = zext i16 %0 to i32
815 %add = add nsw i32 %conv13, %conv4
816 %conv2 = trunc i32 %add to i16
817 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
821 define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
823 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
824 %conv4 = zext i16 %x to i32
825 %add.ptr = getelementptr inbounds i16* %p, i32 %i
826 %0 = load i16* %add.ptr, align 2, !tbaa !2
827 %conv13 = zext i16 %0 to i32
828 %sub = sub nsw i32 %conv13, %conv4
829 %conv2 = trunc i32 %sub to i16
830 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
834 define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
836 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
837 %add.ptr = getelementptr inbounds i16* %p, i32 %i
838 %0 = load i16* %add.ptr, align 2, !tbaa !2
840 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2
844 define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
846 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
847 %add.ptr = getelementptr inbounds i16* %p, i32 %i
848 %0 = load i16* %add.ptr, align 2, !tbaa !2
849 %and3 = and i16 %0, %x
850 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2
854 define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
856 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
857 %add.ptr = getelementptr inbounds i16* %p, i32 %i
858 %0 = load i16* %add.ptr, align 2, !tbaa !2
859 %conv2 = zext i16 %0 to i32
860 %and = and i32 %conv2, 65503
861 %conv1 = trunc i32 %and to i16
862 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
866 define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
868 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
869 %add.ptr = getelementptr inbounds i16* %p, i32 %i
870 %0 = load i16* %add.ptr, align 2, !tbaa !2
871 %conv2 = zext i16 %0 to i32
872 %or = or i32 %conv2, 128
873 %conv1 = trunc i32 %or to i16
874 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
878 define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind {
880 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
881 %add.ptr = getelementptr inbounds i16* %p, i32 5
882 %0 = load i16* %add.ptr, align 2, !tbaa !2
883 %conv2 = zext i16 %0 to i32
884 %add = add nsw i32 %conv2, 5
885 %conv1 = trunc i32 %add to i16
886 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
890 define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind {
892 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
893 %conv4 = zext i16 %x to i32
894 %add.ptr = getelementptr inbounds i16* %p, i32 5
895 %0 = load i16* %add.ptr, align 2, !tbaa !2
896 %conv13 = zext i16 %0 to i32
897 %add = add nsw i32 %conv13, %conv4
898 %conv2 = trunc i32 %add to i16
899 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
903 define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind {
905 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
906 %conv4 = zext i16 %x to i32
907 %add.ptr = getelementptr inbounds i16* %p, i32 5
908 %0 = load i16* %add.ptr, align 2, !tbaa !2
909 %conv13 = zext i16 %0 to i32
910 %sub = sub nsw i32 %conv13, %conv4
911 %conv2 = trunc i32 %sub to i16
912 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2
916 define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind {
918 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
919 %add.ptr = getelementptr inbounds i16* %p, i32 5
920 %0 = load i16* %add.ptr, align 2, !tbaa !2
922 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2
926 define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind {
928 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
929 %add.ptr = getelementptr inbounds i16* %p, i32 5
930 %0 = load i16* %add.ptr, align 2, !tbaa !2
931 %and3 = and i16 %0, %x
932 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2
936 define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind {
938 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
939 %add.ptr = getelementptr inbounds i16* %p, i32 5
940 %0 = load i16* %add.ptr, align 2, !tbaa !2
941 %conv2 = zext i16 %0 to i32
942 %and = and i32 %conv2, 65503
943 %conv1 = trunc i32 %and to i16
944 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
948 define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind {
950 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
951 %add.ptr = getelementptr inbounds i16* %p, i32 5
952 %0 = load i16* %add.ptr, align 2, !tbaa !2
953 %conv2 = zext i16 %0 to i32
954 %or = or i32 %conv2, 128
955 %conv1 = trunc i32 %or to i16
956 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2
960 define void @memop_signed_int_add5(i32* nocapture %p) nounwind {
962 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
963 %0 = load i32* %p, align 4, !tbaa !3
965 store i32 %add, i32* %p, align 4, !tbaa !3
969 define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind {
971 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
972 %0 = load i32* %p, align 4, !tbaa !3
973 %add = add i32 %0, %x
974 store i32 %add, i32* %p, align 4, !tbaa !3
978 define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind {
980 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
981 %0 = load i32* %p, align 4, !tbaa !3
982 %sub = sub i32 %0, %x
983 store i32 %sub, i32* %p, align 4, !tbaa !3
987 define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind {
989 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
990 %0 = load i32* %p, align 4, !tbaa !3
992 store i32 %or, i32* %p, align 4, !tbaa !3
996 define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind {
998 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
999 %0 = load i32* %p, align 4, !tbaa !3
1000 %and = and i32 %0, %x
1001 store i32 %and, i32* %p, align 4, !tbaa !3
1005 define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind {
1007 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
1008 %0 = load i32* %p, align 4, !tbaa !3
1009 %and = and i32 %0, -33
1010 store i32 %and, i32* %p, align 4, !tbaa !3
1014 define void @memop_signed_int_setbit(i32* nocapture %p) nounwind {
1016 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
1017 %0 = load i32* %p, align 4, !tbaa !3
1018 %or = or i32 %0, 128
1019 store i32 %or, i32* %p, align 4, !tbaa !3
1023 define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
1025 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
1026 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1027 %0 = load i32* %add.ptr, align 4, !tbaa !3
1028 %add = add i32 %0, 5
1029 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1033 define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1035 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
1036 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1037 %0 = load i32* %add.ptr, align 4, !tbaa !3
1038 %add = add i32 %0, %x
1039 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1043 define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1045 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
1046 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1047 %0 = load i32* %add.ptr, align 4, !tbaa !3
1048 %sub = sub i32 %0, %x
1049 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3
1053 define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1055 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
1056 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1057 %0 = load i32* %add.ptr, align 4, !tbaa !3
1059 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1063 define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1065 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
1066 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1067 %0 = load i32* %add.ptr, align 4, !tbaa !3
1068 %and = and i32 %0, %x
1069 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1073 define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
1075 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
1076 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1077 %0 = load i32* %add.ptr, align 4, !tbaa !3
1078 %and = and i32 %0, -33
1079 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1083 define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
1085 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
1086 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1087 %0 = load i32* %add.ptr, align 4, !tbaa !3
1088 %or = or i32 %0, 128
1089 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1093 define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind {
1095 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
1096 %add.ptr = getelementptr inbounds i32* %p, i32 5
1097 %0 = load i32* %add.ptr, align 4, !tbaa !3
1098 %add = add i32 %0, 5
1099 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1103 define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
1105 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
1106 %add.ptr = getelementptr inbounds i32* %p, i32 5
1107 %0 = load i32* %add.ptr, align 4, !tbaa !3
1108 %add = add i32 %0, %x
1109 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1113 define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
1115 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
1116 %add.ptr = getelementptr inbounds i32* %p, i32 5
1117 %0 = load i32* %add.ptr, align 4, !tbaa !3
1118 %sub = sub i32 %0, %x
1119 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3
1123 define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
1125 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
1126 %add.ptr = getelementptr inbounds i32* %p, i32 5
1127 %0 = load i32* %add.ptr, align 4, !tbaa !3
1129 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1133 define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
1135 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
1136 %add.ptr = getelementptr inbounds i32* %p, i32 5
1137 %0 = load i32* %add.ptr, align 4, !tbaa !3
1138 %and = and i32 %0, %x
1139 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1143 define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind {
1145 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
1146 %add.ptr = getelementptr inbounds i32* %p, i32 5
1147 %0 = load i32* %add.ptr, align 4, !tbaa !3
1148 %and = and i32 %0, -33
1149 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1153 define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind {
1155 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
1156 %add.ptr = getelementptr inbounds i32* %p, i32 5
1157 %0 = load i32* %add.ptr, align 4, !tbaa !3
1158 %or = or i32 %0, 128
1159 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1163 define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind {
1165 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
1166 %0 = load i32* %p, align 4, !tbaa !3
1167 %add = add nsw i32 %0, 5
1168 store i32 %add, i32* %p, align 4, !tbaa !3
1172 define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind {
1174 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
1175 %0 = load i32* %p, align 4, !tbaa !3
1176 %add = add nsw i32 %0, %x
1177 store i32 %add, i32* %p, align 4, !tbaa !3
1181 define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind {
1183 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
1184 %0 = load i32* %p, align 4, !tbaa !3
1185 %sub = sub nsw i32 %0, %x
1186 store i32 %sub, i32* %p, align 4, !tbaa !3
1190 define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind {
1192 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
1193 %0 = load i32* %p, align 4, !tbaa !3
1195 store i32 %or, i32* %p, align 4, !tbaa !3
1199 define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind {
1201 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
1202 %0 = load i32* %p, align 4, !tbaa !3
1203 %and = and i32 %0, %x
1204 store i32 %and, i32* %p, align 4, !tbaa !3
1208 define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind {
1210 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
1211 %0 = load i32* %p, align 4, !tbaa !3
1212 %and = and i32 %0, -33
1213 store i32 %and, i32* %p, align 4, !tbaa !3
1217 define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind {
1219 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
1220 %0 = load i32* %p, align 4, !tbaa !3
1221 %or = or i32 %0, 128
1222 store i32 %or, i32* %p, align 4, !tbaa !3
1226 define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
1228 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
1229 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1230 %0 = load i32* %add.ptr, align 4, !tbaa !3
1231 %add = add nsw i32 %0, 5
1232 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1236 define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1238 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
1239 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1240 %0 = load i32* %add.ptr, align 4, !tbaa !3
1241 %add = add nsw i32 %0, %x
1242 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1246 define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1248 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
1249 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1250 %0 = load i32* %add.ptr, align 4, !tbaa !3
1251 %sub = sub nsw i32 %0, %x
1252 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3
1256 define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1258 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
1259 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1260 %0 = load i32* %add.ptr, align 4, !tbaa !3
1262 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1266 define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
1268 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
1269 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1270 %0 = load i32* %add.ptr, align 4, !tbaa !3
1271 %and = and i32 %0, %x
1272 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1276 define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
1278 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
1279 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1280 %0 = load i32* %add.ptr, align 4, !tbaa !3
1281 %and = and i32 %0, -33
1282 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1286 define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
1288 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
1289 %add.ptr = getelementptr inbounds i32* %p, i32 %i
1290 %0 = load i32* %add.ptr, align 4, !tbaa !3
1291 %or = or i32 %0, 128
1292 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1296 define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind {
1298 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
1299 %add.ptr = getelementptr inbounds i32* %p, i32 5
1300 %0 = load i32* %add.ptr, align 4, !tbaa !3
1301 %add = add nsw i32 %0, 5
1302 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1306 define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
1308 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
1309 %add.ptr = getelementptr inbounds i32* %p, i32 5
1310 %0 = load i32* %add.ptr, align 4, !tbaa !3
1311 %add = add nsw i32 %0, %x
1312 store i32 %add, i32* %add.ptr, align 4, !tbaa !3
1316 define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
1318 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
1319 %add.ptr = getelementptr inbounds i32* %p, i32 5
1320 %0 = load i32* %add.ptr, align 4, !tbaa !3
1321 %sub = sub nsw i32 %0, %x
1322 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3
1326 define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
1328 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
1329 %add.ptr = getelementptr inbounds i32* %p, i32 5
1330 %0 = load i32* %add.ptr, align 4, !tbaa !3
1332 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1336 define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
1338 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
1339 %add.ptr = getelementptr inbounds i32* %p, i32 5
1340 %0 = load i32* %add.ptr, align 4, !tbaa !3
1341 %and = and i32 %0, %x
1342 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1346 define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind {
1348 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
1349 %add.ptr = getelementptr inbounds i32* %p, i32 5
1350 %0 = load i32* %add.ptr, align 4, !tbaa !3
1351 %and = and i32 %0, -33
1352 store i32 %and, i32* %add.ptr, align 4, !tbaa !3
1356 define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind {
1358 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
1359 %add.ptr = getelementptr inbounds i32* %p, i32 5
1360 %0 = load i32* %add.ptr, align 4, !tbaa !3
1361 %or = or i32 %0, 128
1362 store i32 %or, i32* %add.ptr, align 4, !tbaa !3
1366 !0 = metadata !{metadata !"omnipotent char", metadata !1}
1367 !1 = metadata !{metadata !"Simple C/C++ TBAA"}
1368 !2 = metadata !{metadata !"short", metadata !0}
1369 !3 = metadata !{metadata !"int", metadata !0}