1 # RUN: llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s | FileCheck %s
2 # This test verifies that the MIR parser can parse target index operands.
6 %struct.foo = type { float, [5 x i32] }
8 @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4
10 define void @float(float addrspace(1)* %out, i32 %index) #0 {
12 %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
13 %1 = load float, float addrspace(2)* %0
14 store float %1, float addrspace(1)* %out
18 define void @float2(float addrspace(1)* %out, i32 %index) #0 {
20 %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
21 %1 = load float, float addrspace(2)* %0
22 store float %1, float addrspace(1)* %out
26 declare { i1, i64 } @llvm.SI.if(i1)
28 declare { i1, i64 } @llvm.SI.else(i64)
30 declare i64 @llvm.SI.break(i64)
32 declare i64 @llvm.SI.if.break(i1, i64)
34 declare i64 @llvm.SI.else.break(i64, i64)
36 declare i1 @llvm.SI.loop(i64)
38 declare void @llvm.SI.end.cf(i64)
40 attributes #0 = { "target-cpu"="SI" }
45 tracksSubRegLiveness: true
47 - { reg: '%sgpr0_sgpr1' }
53 liveins: [ '%sgpr0_sgpr1' ]
55 - '%sgpr2_sgpr3 = S_GETPC_B64'
56 # CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
57 - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc'
58 - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
59 - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
60 - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
61 - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
62 - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
63 - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
64 - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
65 - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
66 - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
67 - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
68 - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
69 - '%sgpr7 = S_MOV_B32 61440'
70 - '%sgpr6 = S_MOV_B32 -1'
71 - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
72 - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
77 tracksSubRegLiveness: true
79 - { reg: '%sgpr0_sgpr1' }
85 liveins: [ '%sgpr0_sgpr1' ]
87 - '%sgpr2_sgpr3 = S_GETPC_B64'
88 # CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
89 - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc'
90 - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
91 - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
92 - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
93 - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
94 - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
95 - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
96 - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
97 - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
98 - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
99 - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
100 - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
101 - '%sgpr7 = S_MOV_B32 61440'
102 - '%sgpr6 = S_MOV_B32 -1'
103 - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
104 - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'