1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s
2 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
4 @ub1 = common global i8 0, align 1
5 @ub2 = common global i8 0, align 1
6 @ub3 = common global i8 0, align 1
7 @uc1 = common global i8 0, align 1
8 @uc2 = common global i8 0, align 1
9 @uc3 = common global i8 0, align 1
10 @us1 = common global i16 0, align 2
11 @us2 = common global i16 0, align 2
12 @us3 = common global i16 0, align 2
13 @ub = common global i8 0, align 1
14 @uc = common global i8 0, align 1
15 @us = common global i16 0, align 2
16 @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
17 @ui = common global i32 0, align 4
18 @ui1 = common global i32 0, align 4
19 @ui2 = common global i32 0, align 4
20 @ui3 = common global i32 0, align 4
22 ; Function Attrs: noinline nounwind
23 define void @andUb() #0 {
25 %0 = load i8, i8* @ub1, align 1
26 %1 = load i8, i8* @ub2, align 1
27 %conv0 = trunc i8 %0 to i1
28 %conv1 = trunc i8 %1 to i1
29 %and0 = and i1 %conv1, %conv0
30 %conv3 = zext i1 %and0 to i8
31 store i8 %conv3, i8* @ub, align 1, !tbaa !2
32 ; CHECK-LABEL: .ent andUb
33 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
34 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
35 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
36 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
37 ; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
38 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
39 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
40 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
41 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
43 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
47 ; Function Attrs: noinline nounwind
48 define void @andUb0() #0 {
50 %0 = load i8, i8* @ub1, align 1, !tbaa !2
51 %conv = trunc i8 %0 to i1
52 %and = and i1 %conv, 0
53 %conv1 = zext i1 %and to i8
54 store i8 %conv1, i8* @ub, align 1, !tbaa !2
55 ; CHECK-LABEL: .ent andUb0
56 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
57 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
58 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
59 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
60 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
61 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
62 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero
63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
64 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
69 ; Function Attrs: noinline nounwind
70 define void @andUb1() #0 {
72 %0 = load i8, i8* @ub1, align 1, !tbaa !2
73 %conv = trunc i8 %0 to i1
74 %and = and i1 %conv, 1
75 %conv1 = zext i1 %and to i8
76 store i8 %conv1, i8* @ub, align 1, !tbaa !2
77 ; CHECK-LABEL: .ent andUb1
78 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
79 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
80 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
81 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
82 ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
83 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
84 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
85 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
86 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
87 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
92 ; Function Attrs: noinline nounwind
93 define void @orUb() #0 {
95 %0 = load i8, i8* @ub1, align 1
96 %1 = load i8, i8* @ub2, align 1
97 %conv0 = trunc i8 %0 to i1
98 %conv1 = trunc i8 %1 to i1
99 %or0 = or i1 %conv1, %conv0
100 %conv3 = zext i1 %or0 to i8
101 store i8 %conv3, i8* @ub, align 1, !tbaa !2
102 ; CHECK-LABEL: .ent orUb
103 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
104 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
105 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
106 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
107 ; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
108 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
109 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
110 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
111 ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
112 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
113 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
117 ; Function Attrs: noinline nounwind
118 define void @orUb0() #0 {
120 %0 = load i8, i8* @ub1, align 1, !tbaa !2
121 %conv = trunc i8 %0 to i1
123 %conv1 = zext i1 %or to i8
124 store i8 %conv1, i8* @ub, align 1, !tbaa !2
125 ; CHECK-LABEL: .ent orUb0
126 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
127 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
128 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
129 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
130 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
131 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
132 ; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1
133 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
138 ; Function Attrs: noinline nounwind
139 define void @orUb1() #0 {
141 %0 = load i8, i8* @ub1, align 1, !tbaa !2
142 %conv = trunc i8 %0 to i1
144 %conv1 = zext i1 %or to i8
145 store i8 %conv1, i8* @ub, align 1, !tbaa !2
146 ; CHECK-LABEL: .ent orUb1
147 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
148 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
149 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
150 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
151 ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
152 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
153 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
154 ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
155 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
156 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
161 ; Function Attrs: noinline nounwind
162 define void @xorUb() #0 {
164 %0 = load i8, i8* @ub1, align 1
165 %1 = load i8, i8* @ub2, align 1
166 %conv0 = trunc i8 %0 to i1
167 %conv1 = trunc i8 %1 to i1
168 %xor0 = xor i1 %conv1, %conv0
169 %conv3 = zext i1 %xor0 to i8
170 store i8 %conv3, i8* @ub, align 1, !tbaa !2
171 ; CHECK-LABEL: .ent xorUb
172 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
173 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
174 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
175 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
176 ; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]])
177 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
178 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
179 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
180 ; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
181 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
182 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
186 ; Function Attrs: noinline nounwind
187 define void @xorUb0() #0 {
189 %0 = load i8, i8* @ub1, align 1, !tbaa !2
190 %conv = trunc i8 %0 to i1
191 %xor = xor i1 %conv, 0
192 %conv1 = zext i1 %xor to i8
193 store i8 %conv1, i8* @ub, align 1, !tbaa !2
194 ; CHECK-LABEL: .ent xorUb0
195 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
196 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
197 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
198 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
199 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
200 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
201 ; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $zero
202 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
203 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
208 ; Function Attrs: noinline nounwind
209 define void @xorUb1() #0 {
211 %0 = load i8, i8* @ub1, align 1, !tbaa !2
212 %conv = trunc i8 %0 to i1
213 %xor = xor i1 %conv, 1
214 %conv1 = zext i1 %xor to i8
215 store i8 %conv1, i8* @ub, align 1, !tbaa !2
216 ; CHECK-LABEL: .ent xorUb1
217 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
218 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
219 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
220 ; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]])
221 ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1
222 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]])
223 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
224 ; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
225 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
226 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
231 ; Function Attrs: noinline nounwind
232 define void @andUc() #0 {
234 %0 = load i8, i8* @uc1, align 1, !tbaa !2
235 %1 = load i8, i8* @uc2, align 1, !tbaa !2
236 %and3 = and i8 %1, %0
237 store i8 %and3, i8* @uc, align 1, !tbaa !2
238 ; CHECK-LABEL: .ent andUc
239 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
240 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
241 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
242 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
243 ; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
244 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
245 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
246 ; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
247 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC2]], $[[UB1]]
248 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
252 ; Function Attrs: noinline nounwind
253 define void @andUc0() #0 {
255 %0 = load i8, i8* @uc1, align 1, !tbaa !2
257 store i8 %and, i8* @uc, align 1, !tbaa !2
258 ; CHECK-LABEL: .ent andUc0
259 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
260 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
261 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
262 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
263 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
264 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
265 ; CHECK-DAG: addiu $[[CONST_67:[0-9]+]], $zero, 67
266 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_67]]
267 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
272 ; Function Attrs: noinline nounwind
273 define void @andUc1() #0 {
275 %0 = load i8, i8* @uc1, align 1, !tbaa !2
276 %and = and i8 %0, 167
277 store i8 %and, i8* @uc, align 1, !tbaa !2
278 ; CHECK-LABEL: .ent andUc1
279 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
280 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
281 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
282 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
283 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
284 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
285 ; CHECK-DAG: addiu $[[CONST_Neg89:[0-9]+]], $zero, -89
286 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_Neg89]]
287 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
292 ; Function Attrs: noinline nounwind
293 define void @orUc() #0 {
295 %0 = load i8, i8* @uc1, align 1, !tbaa !2
296 %1 = load i8, i8* @uc2, align 1, !tbaa !2
298 store i8 %or3, i8* @uc, align 1, !tbaa !2
299 ; CHECK-LABEL: .ent orUc
300 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
301 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
302 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
303 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
304 ; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
305 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
306 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
307 ; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
308 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]
309 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
314 ; Function Attrs: noinline nounwind
315 define void @orUc0() #0 {
317 %0 = load i8, i8* @uc1, align 1, !tbaa !2
319 store i8 %or, i8* @uc, align 1, !tbaa !2
320 ; CHECK-LABEL: .ent orUc0
321 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
322 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
323 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
324 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
325 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
326 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
327 ; CHECK-DAG: addiu $[[CONST_69:[0-9]+]], $zero, 69
328 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_69]]
329 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
334 ; Function Attrs: noinline nounwind
335 define void @orUc1() #0 {
337 %0 = load i8, i8* @uc1, align 1, !tbaa !2
339 store i8 %or, i8* @uc, align 1, !tbaa !2
340 ; CHECK-LABEL: .ent orUc1
341 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
342 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
343 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
344 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
345 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
346 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
347 ; CHECK-DAG: addiu $[[CONST_neg18:[0-9]+]], $zero, -18
348 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_neg18]]
349 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
354 ; Function Attrs: noinline nounwind
355 define void @xorUc() #0 {
357 %0 = load i8, i8* @uc1, align 1, !tbaa !2
358 %1 = load i8, i8* @uc2, align 1, !tbaa !2
359 %xor3 = xor i8 %1, %0
360 store i8 %xor3, i8* @uc, align 1, !tbaa !2
361 ; CHECK-LABEL: .ent xorUc
362 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
363 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
364 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
365 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
366 ; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]])
367 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
368 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
369 ; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
370 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]
371 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
376 ; Function Attrs: noinline nounwind
377 define void @xorUc0() #0 {
379 %0 = load i8, i8* @uc1, align 1, !tbaa !2
381 store i8 %xor, i8* @uc, align 1, !tbaa !2
382 ; CHECK-LABEL: .ent xorUc0
383 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
384 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
385 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
386 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
387 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
388 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
389 ; CHECK-DAG: addiu $[[CONST_23:[0-9]+]], $zero, 23
390 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_23]]
391 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
396 ; Function Attrs: noinline nounwind
397 define void @xorUc1() #0 {
399 %0 = load i8, i8* @uc1, align 1, !tbaa !2
400 %xor = xor i8 %0, 120
401 store i8 %xor, i8* @uc, align 1, !tbaa !2
402 ; CHECK-LABEL: .ent xorUc1
403 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
404 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
405 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
406 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
407 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
408 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
409 ; CHECK-DAG: addiu $[[CONST_120:[0-9]+]], $zero, 120
410 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_120]]
411 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
416 ; Function Attrs: noinline nounwind
417 define void @andUs() #0 {
419 %0 = load i16, i16* @us1, align 2, !tbaa !5
420 %1 = load i16, i16* @us2, align 2, !tbaa !5
421 %and3 = and i16 %1, %0
422 store i16 %and3, i16* @us, align 2, !tbaa !5
423 ; CHECK-LABEL: .ent andUs
424 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
425 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
426 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
427 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
428 ; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
429 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
430 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
431 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
432 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[US2]], $[[UB1]]
433 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
438 ; Function Attrs: noinline nounwind
439 define void @andUs0() #0 {
441 %0 = load i16, i16* @us1, align 2, !tbaa !5
442 %and = and i16 %0, 4660
443 store i16 %and, i16* @us, align 2, !tbaa !5
444 ; CHECK-LABEL: .ent andUs0
445 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
446 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
447 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
448 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
449 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
450 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
451 ; CHECK-DAG: addiu $[[CONST_4660:[0-9]+]], $zero, 4660
452 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_4660]]
453 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
458 ; Function Attrs: noinline nounwind
459 define void @andUs1() #0 {
461 %0 = load i16, i16* @us1, align 2, !tbaa !5
462 %and = and i16 %0, 61351
463 store i16 %and, i16* @us, align 2, !tbaa !5
464 ; CHECK-LABEL: .ent andUs1
465 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
466 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
467 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
468 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
469 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
470 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
471 ; CHECK-DAG: addiu $[[CONST_Neg4185:[0-9]+]], $zero, -4185
472 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg4185]]
473 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
478 ; Function Attrs: noinline nounwind
479 define void @orUs() #0 {
481 %0 = load i16, i16* @us1, align 2, !tbaa !5
482 %1 = load i16, i16* @us2, align 2, !tbaa !5
484 store i16 %or3, i16* @us, align 2, !tbaa !5
485 ; CHECK-LABEL: .ent orUs
486 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
487 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
488 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
489 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
490 ; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
491 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
492 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
493 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
494 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[US2]], $[[US1]]
495 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
500 ; Function Attrs: noinline nounwind
501 define void @orUs0() #0 {
503 %0 = load i16, i16* @us1, align 2, !tbaa !5
504 %or = or i16 %0, 17666
505 store i16 %or, i16* @us, align 2, !tbaa !5
509 ; Function Attrs: noinline nounwind
510 define void @orUs1() #0 {
512 %0 = load i16, i16* @us1, align 2, !tbaa !5
513 %or = or i16 %0, 60945
514 store i16 %or, i16* @us, align 2, !tbaa !5
515 ; CHECK-LABEL: .ent orUs1
516 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
517 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
518 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
519 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
520 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
521 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
522 ; CHECK-DAG: addiu $[[CONST_neg4591:[0-9]+]], $zero, -4591
523 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_neg4591]]
524 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
529 ; Function Attrs: noinline nounwind
530 define void @xorUs() #0 {
532 %0 = load i16, i16* @us1, align 2, !tbaa !5
533 %1 = load i16, i16* @us2, align 2, !tbaa !5
534 %xor3 = xor i16 %1, %0
535 store i16 %xor3, i16* @us, align 2, !tbaa !5
536 ; CHECK-LABEL: .ent xorUs
537 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
538 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
539 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
540 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
541 ; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
542 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
543 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
544 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
545 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US2]], $[[US1]]
546 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
551 ; Function Attrs: noinline nounwind
552 define void @xorUs0() #0 {
554 %0 = load i16, i16* @us1, align 2, !tbaa !5
555 %xor = xor i16 %0, 6062
556 store i16 %xor, i16* @us, align 2, !tbaa !5
557 ; CHECK-LABEL: .ent xorUs0
558 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
559 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
560 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
561 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
562 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
563 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
564 ; CHECK-DAG: addiu $[[CONST_6062:[0-9]+]], $zero, 6062
565 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_6062]]
566 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
572 ; Function Attrs: noinline nounwind
573 define void @xorUs1() #0 {
575 %0 = load i16, i16* @us1, align 2, !tbaa !5
576 %xor = xor i16 %0, 60024
577 store i16 %xor, i16* @us, align 2, !tbaa !5
578 ; CHECK-LABEL: .ent xorUs1
579 ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
580 ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
581 ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
582 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
583 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
584 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
585 ; CHECK-DAG: addiu $[[CONST_Neg5512:[0-9]+]], $zero, -5512
586 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg5512]]
587 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
592 attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
593 attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
594 attributes #2 = { nounwind }
596 !llvm.module.flags = !{!0}
599 !0 = !{i32 1, !"PIC Level", i32 2}
600 !1 = !{!"clang version 3.7.0 (trunk)"}
601 !2 = !{!3, !3, i64 0}
602 !3 = !{!"omnipotent char", !4, i64 0}
603 !4 = !{!"Simple C/C++ TBAA"}
604 !5 = !{!6, !6, i64 0}
605 !6 = !{!"short", !3, i64 0}